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    CODE DESIGN AND IMPLEMENTATION IMPROVEMENTS FOR LOW DENSITY PARITY CHECK CODES FOR MULTIPLE-INPUT MULTIPLE-OUTPUT CHANNELS
    31.
    发明申请
    CODE DESIGN AND IMPLEMENTATION IMPROVEMENTS FOR LOW DENSITY PARITY CHECK CODES FOR MULTIPLE-INPUT MULTIPLE-OUTPUT CHANNELS 有权
    用于多输入多输出通道的低密度奇偶校验码的代码设计和实现改进

    公开(公告)号：US20100192038A1

    公开(公告)日：2010-07-29

    申请号：US12753528

    申请日：2010-04-02

    申请人： Mustafa Eroz ,  Lin-Nan Lee ,  Feng-Wen Sun

    发明人： Mustafa Eroz ,  Lin-Nan Lee ,  Feng-Wen Sun

    IPC分类号： H03M13/05 ,  G06F11/10

    CPC分类号： H03M13/1185 ,  H03M13/1137 ,  H03M13/152 ,  H03M13/2906 ,  H04B7/02 ,  H04L1/005 ,  H04L1/0057 ,  H04L1/0625

    摘要： Methods and systems for designing LDPC codes are disclosed. A method in accordance with the present invention comprises configuring a plurality of parallel accumulation engines, a number of the plurality of parallel accumulation engines equal to M, accumulating a first information bit at a first set of specific parity bit addresses using the plurality of parallel accumulation engines, increasing a parity bit address for each member of the first set of specific parity bit addresses by a pre-determined offset for each new information bit, accumulating subsequent information bits at parity bit addresses that are offset from the specific parity bit addresses by a pre-determined offset until an M+1 information bit is reached, accumulating the next M information bits at a second set of specific parity bit addresses using the plurality of parallel accumulation engines, increasing a parity bit address for each member of the second set of specific parity bit addresses by the pre-determined offset for each new information bit; and repeating accumulating and increasing the addresses until the information bits are exhausted.

    摘要翻译： 公开了用于设计LDPC码的方法和系统。 根据本发明的方法包括配置多个并行累积引擎，多个并行累加引擎中的多个等于M，使用多个并行累加累积第一组特定奇偶校验位地址处的第一信息位 引擎，通过针对每个新信息位的预定偏移增加第一组特定奇偶校验位地址的每个成员的奇偶校验位地址，在与特定奇偶校验位地址偏移的奇偶校验位地址处累积后续信息比特 预定的偏移量直到达到M + 1信息位，使用多个并行累积引擎在第二组特定奇偶校验位地址累积下一个M个信息位，增加第二组的每个成员的奇偶校验位地址 特定奇偶校验位地址由每个新信息位的预定偏移量; 并重复累积和增加地址直到信息位耗尽。

    Bit labeling for amplitude phase shift constellation used with low density parity check (LDPC) codes
    32.
    发明授权
    Bit labeling for amplitude phase shift constellation used with low density parity check (LDPC) codes 有权
    用于与低密度奇偶校验（LDPC）码一起使用的振幅相移星座的位标记

    公开(公告)号：US07577207B2

    公开(公告)日：2009-08-18

    申请号：US11186265

    申请日：2005-07-21

    申请人： Mustafa Eroz ,  Feng-Wen Sun ,  Lin-Nan Lee

    发明人： Mustafa Eroz ,  Feng-Wen Sun ,  Lin-Nan Lee

    IPC分类号： H04L5/12 ,  G11C29/00

    CPC分类号： H03M13/13 ,  H03M13/1137 ,  H03M13/1165 ,  H03M13/1515 ,  H03M13/152 ,  H03M13/255 ,  H03M13/2906 ,  H03M13/2927 ,  H03M13/6306 ,  H04L1/0041 ,  H04L1/0057 ,  H04L1/0071 ,  H04L27/186 ,  H04L27/2053

    摘要： An approach is provided for bit labeling of a signal constellation. A transmitter generates encoded signals using, according to one embodiment, a structured parity check matrix of a Low Density Parity Check (LDPC) code. The transmitter includes an encoder for transforming an input message into a codeword represented by a plurality of set of bits. The transmitter includes logic for mapping non-sequentially (e.g., interleaving) one set of bits into a higher order constellation (Quadrature Phase Shift Keying (QPSK), 8-PSK, 16-APSK (Amplitude Phase Shift Keying), 32-APSK, etc.), wherein a symbol of the higher order constellation corresponding to the one set of bits is output based on the mapping.

    摘要翻译： 提供了一种用于信号星座的位标记的方法。 根据一个实施例，发射机使用低密度奇偶校验（LDPC）码的结构奇偶校验矩阵来生成编码信号。 发射机包括用于将输入消息变换成由多个位组表示的码字的编码器。 发射机包括用于将一组比特的非顺序（例如，交织）映射成高阶星座（正交相移键控（QPSK），8-PSK，16-APSK（振幅相移键控），32-APSK， 等等），其中基于该映射输出对应于该一组比特的较高阶星座的符号。

    ENCODING LOW DENSITY PARITY CHECK (LDPC) CODES THROUGH AN LDPC DECODER
    33.
    发明申请
    ENCODING LOW DENSITY PARITY CHECK (LDPC) CODES THROUGH AN LDPC DECODER 有权
    通过LDPC解码器编码低密度奇偶校验（LDPC）编码

    公开(公告)号：US20080313523A1

    公开(公告)日：2008-12-18

    申请号：US12186485

    申请日：2008-08-05

    申请人： Feng-Wen Sun ,  Mustafa Eroz ,  Lin-Nan Lee

    发明人： Feng-Wen Sun ,  Mustafa Eroz ,  Lin-Nan Lee

    IPC分类号： H03M13/11 ,  G06F11/10

    CPC分类号： H03M13/1102 ,  H03M13/2957

    摘要： An approach is providing for supporting broadcast transmission of low density parity check (LDPC) coded signals. A receiver includes a decoder configured to decode an LDPC signal to output a decoded signal. The decoder is further configured to operate as an encoder; as such, interference cancellation can be implemented by the encoder re-encoded the received decoded signal. The above approach has particular applicability to satellite broadcast systems.

    摘要翻译： 一种方法是提供支持低密度奇偶校验（LDPC）编码信号的广播传输。 接收机包括：解码器，被配置为解码LDPC信号以输出解码信号。 解码器还被配置为作为编码器操作; 因此，干扰消除可以由编码器重新编码接收的解码信号来实现。 上述方法对卫星广播系统具有特别的适用性。

    Method and system for generating parallel decodable low density parity check (LDPC) codes
    35.
    发明授权
    Method and system for generating parallel decodable low density parity check (LDPC) codes 有权
    用于产生并行解码低密度奇偶校验（LDPC）码的方法和系统

    公开(公告)号：US07296208B2

    公开(公告)日：2007-11-13

    申请号：US10882705

    申请日：2004-07-01

    申请人： Feng-Wen Sun ,  Mustafa Eroz ,  Lin-Nan Lee

    发明人： Feng-Wen Sun ,  Mustafa Eroz ,  Lin-Nan Lee

    IPC分类号： H03M13/11

    CPC分类号： H03M13/1168 ,  H03M13/1137 ,  H03M13/1165 ,  H03M13/6505

    摘要： An approach is provided for efficiently decoding low density parity check (LDPC) codes. An LDPC decoder includes a memory for storing a mapped matrix that satisfies a plurality of parallel decodable conditions for permitting a lumped memory structure. Additionally, the decoder includes a parallel processors accessing edge values from the stored mapped matrix decode the LDPC codes. The above approach has particular applicability to satellite broadcast systems.

    摘要翻译： 提供了一种用于有效解码低密度奇偶校验（LDPC）码的方法。 LDPC解码器包括存储器，用于存储满足用于允许集中存储器结构的多个并行可解码条件的映射矩阵。 此外，解码器包括从存储的映射矩阵访问边缘值的并行处理器解码LDPC码。 上述方法对卫星广播系统具有特别的适用性。

    Method and apparatus for providing higher order modulation that is backwards compatible with quaternary phase shift keying (QPSK) or offset quaternary phase shift keying (OQPSK)
    36.
    发明授权
    Method and apparatus for providing higher order modulation that is backwards compatible with quaternary phase shift keying (QPSK) or offset quaternary phase shift keying (OQPSK) 有权
    用于提供与四相相移键控（QPSK）或偏移四相相移键控（OQPSK）向后兼容的更高阶调制的方法和装置，

    公开(公告)号：US07260159B2

    公开(公告)日：2007-08-21

    申请号：US10142703

    申请日：2002-05-10

    申请人： Lin-Nan Lee ,  Feng-Wen Sun ,  Mustafa Eroz ,  Yimin Jiang

    发明人： Lin-Nan Lee ,  Feng-Wen Sun ,  Mustafa Eroz ,  Yimin Jiang

    IPC分类号： H03D3/22 ,  H04L27/22

    CPC分类号： H04L27/3488 ,  H04L27/183

    摘要： A method and apparatus for providing an asymmetrical backwards compatible communications signal that is capable of being decoded by QPSK and OQPSK receivers as well as PSK and QAM receivers is provided. The invention comprises a timing error accumulator coupled to a first bit stream. The first bit stream includes content that is common to the QPSK/OQPSK receiver and to the PSK/QAM receiver. A phase error accumulator is coupled to a second bit stream and adjusts the phase of symbols in the second bit stream. A phase and timing error compensator is coupled to the phase error accumulator and the timing error accumulator and adjusts the first and second bit streams received from the phase error accumulator and the timing error accumulator in order to reduce timing and phase errors. A higher order modulator coupled to the phase and timing error compensator is also provided. The higher order modulator processes the first and second bit streams to provide the asymmetrical backwards compatible signal.

    摘要翻译： 提供一种提供能够被QPSK和OQPSK接收机以及PSK和QAM接收机解码的不对称向后兼容通信信号的方法和装置。 本发明包括耦合到第一位流的定时误差累加器。 第一比特流包括对于QPSK / OQPSK接收机和PSK / QAM接收机是共同的内容。 相位误差累加器被耦合到第二比特流并且调整第二比特流中的符号的相位。 相位和定时误差补偿器耦合到相位误差累加器和定时误差累加器，并调整从相位误差累加器和定时误差累加器接收的第一和第二比特流，以减少定时和相位误差。 还提供耦合到相位和定时误差补偿器的高阶调制器。 高阶调制器处理第一和第二比特流以提供不对称的向后兼容信号。

    Method and system for generating parallel decodable low density parity check (LDPC) codes
    39.
    发明授权
    Method and system for generating parallel decodable low density parity check (LDPC) codes 有权
    用于产生并行解码低密度奇偶校验（LDPC）码的方法和系统

    公开(公告)号：US08140931B2

    公开(公告)日：2012-03-20

    申请号：US11938095

    申请日：2007-11-09

    申请人： Mustafa Eroz ,  Feng-Wen Sun ,  Lin-Nan Lee

    发明人： Mustafa Eroz ,  Feng-Wen Sun ,  Lin-Nan Lee

    IPC分类号： H03M13/00

    CPC分类号： H03M13/1165 ,  H03M13/1137

    摘要： An approach is provided for efficiently decoding low density parity check (LDPC) codes. A plurality of parallel processors decode the LDPC codes mapped by accessing a mapped matrix in a memory structure. The mapped matrix is constructed based on a parity check matrix of the LDPC codes. No two different entries in an identical row of the mapped matrix connects to identical bit nodes or identical check nodes.

    摘要翻译： 提供了一种用于有效解码低密度奇偶校验（LDPC）码的方法。 多个并行处理器通过访问存储器结构中的映射矩阵来解码映射的LDPC码。 基于LDPC码的奇偶校验矩阵构造映射矩阵。 映射矩阵的相同行中没有两个不同的条目连接到相同的位节点或相同的校验节点。