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    EARLY RELEASE OF RESOURCES IN RAY TRACING HARDWARE
    32.
    发明公开
    EARLY RELEASE OF RESOURCES IN RAY TRACING HARDWARE 审中-公开

    公开(公告)号：US20240104826A1

    公开(公告)日：2024-03-28

    申请号：US18509038

    申请日：2023-11-14

    Applicant: NVIDIA Corporation

    Inventor： Gregory MUTHLER ,  John BURGESS ,  Ronald Charles BABICH, JR. ,  William Parsons Newhall, JR.

    IPC: G06T15/06 ,  G06F9/48 ,  G06F9/50 ,  G06T17/10

    CPC classification number: G06T15/06 ,  G06F9/48 ,  G06F9/5027 ,  G06T17/10 ,  G06T2210/21

    Abstract: Techniques are disclosed for improving the throughput of ray intersection or visibility queries performed by a ray tracing hardware accelerator. Throughput is improved, for example, by releasing allocated resources before ray visibility query results are reported by the hardware accelerator. The allocated resources are released when the ray visibility query results can be stored in a compressed format outside of the allocated resources. When reporting the ray visibility query results, the results are reconstructed based on the results stored in the compressed format. The compressed format storage can be used for ray visibility queries that return no intersections or terminate on any hit ray visibility query. One or more individual components of allocated resources can also be independently deallocated based on the type of data to be returned and/or results of the ray visibility query.

    EFFICIENCY OF RAY-BOX TESTS
    33.
    发明公开
    EFFICIENCY OF RAY-BOX TESTS 审中-公开

    公开(公告)号：US20240095996A1

    公开(公告)日：2024-03-21

    申请号：US17946509

    申请日：2022-09-16

    Applicant: NVIDIA Corporation

    Inventor： Gregory MUTHLER ,  John BURGESS ,  Eric ENDERTON ,  Nikhil DIXIT ,  Josh NOEL

    IPC: G06T15/06

    CPC classification number: G06T15/06

    Abstract: To improve the efficiency of bounding volumes in a hardware based ray tracer, we employ a sheared axis-aligned bounding box to approximate an oriented bounding box typically defined by rotations. To achieve this, the bounding volume hierarchy builder shears an axis-aligned box to fit tightly around its enclosed oriented geometry in top level or bottom level space, then computes the inverse shear transform. The bounds are still stored as axis-aligned boxes in memory, now defined in the new sheared coordinate system, along with the derived parameters to transform a ray into the sheared coordinate system before testing intersection with the boxes. The ray-bounding volume intersection test is performed as usual, just in the new sheared coordinate system. Additional efficiencies are gained by constraining the number of shear dimensions, constraining the shear transform coefficients to a quantized list, sharing a shear transform across a collection of bounds, performing a shear transform only for ray-bounds testing and not for ray-geometry intersection testing, and adding a specialized shear transform calculator/accelerator to the hardware.

    EARLY RELEASE OF RESOURCES IN RAY TRACING HARDWARE
    34.
    发明申请
    EARLY RELEASE OF RESOURCES IN RAY TRACING HARDWARE 有权

    公开(公告)号：US20230041724A1

    公开(公告)日：2023-02-09

    申请号：US17968485

    申请日：2022-10-18

    Applicant: NVIDIA Corporation

    Inventor： Gregory MUTHLER ,  John BURGESS ,  Ronald Charles BABICH, JR. ,  William Parsons Newhall, JR.

    IPC: G06T15/06 ,  G06T17/10 ,  G06F9/48 ,  G06F9/50

    Abstract: Techniques are disclosed for improving the throughput of ray intersection or visibility queries performed by a ray tracing hardware accelerator. Throughput is improved, for example, by releasing allocated resources before ray visibility query results are reported by the hardware accelerator. The allocated resources are released when the ray visibility query results can be stored in a compressed format outside of the allocated resources. When reporting the ray visibility query results, the results are reconstructed based on the results stored in the compressed format. The compressed format storage can be used for ray visibility queries that return no intersections or terminate on any hit ray visibility query. One or more individual components of allocated resources can also be independently deallocated based on the type of data to be returned and/or results of the ray visibility query.

    Enhanced Techniques for Traversing Ray Tracing Acceleration Structures
    35.
    发明申请
    Enhanced Techniques for Traversing Ray Tracing Acceleration Structures 有权

    公开(公告)号：US20220292760A1

    公开(公告)日：2022-09-15

    申请号：US17829954

    申请日：2022-06-01

    Applicant: NVIDIA Corporation

    Inventor： Gregory MUTHLER ,  John BURGESS

    IPC: G06T15/06 ,  G06T15/08 ,  G06F9/50 ,  G06F9/30 ,  G06T17/00

    Abstract: Enhanced techniques applicable to a ray tracing hardware accelerator for traversing a hierarchical acceleration structure are disclosed. For example, traversal efficiency is improved by combining programmable traversals based on ray operations with per-node static configurations that modify traversal behavior. The per-node static configurations enable creators of acceleration data structures to optimize for potential traversals without necessarily requiring detailed information about ray characteristics and ray operations used when traversing the acceleration structure. Moreover, by providing for selective exclusion of certain nodes using per-node static configurations, less memory is needed to express an acceleration structure that includes, for example, different geometric levels of details corresponding to a single object.

    TECHNIQUES FOR TRAVERSING DATA EMPLOYED IN RAY TRACING
    36.
    发明申请
    TECHNIQUES FOR TRAVERSING DATA EMPLOYED IN RAY TRACING 有权

    公开(公告)号：US20220189099A1

    公开(公告)日：2022-06-16

    申请号：US17689268

    申请日：2022-03-08

    Applicant: NVIDIA Corporation

    Inventor： Gregory MUTHLER ,  John BURGESS

    IPC: G06T15/06 ,  G06N3/02 ,  G06T15/00

    Abstract: Ray tracing hardware accelerators supporting multiple specifiers for controlling the traversal of a ray tracing acceleration data structure are disclosed. For example, traversal efficiency and complex ray tracing effects can be achieved by specifying traversals through such data structures using both programmable ray operations and explicit node masking. The explicit node masking utilizes dedicated fields in the ray and in nodes of the acceleration data structure to control traversals. Ray operations, however, are programmable per ray using opcodes and additional parameters to control traversals. Traversal efficiency is improved by enabling more aggressive culling of parts of the data structure based on the combination of explicit node masking and programmable ray operations. More complex ray tracing effects are enabled by providing for dynamic selection of nodes based on individual ray characteristics.

    TECHNIQUES FOR TRAVERSING DATA EMPLOYED IN RAY TRACING
    37.
    发明申请
    TECHNIQUES FOR TRAVERSING DATA EMPLOYED IN RAY TRACING 有权

    公开(公告)号：US20210390757A1

    公开(公告)日：2021-12-16

    申请号：US16897909

    申请日：2020-06-10

    Applicant: NVIDIA Corporation

    Inventor： Gregory MUTHLER ,  John BURGESS

    IPC: G06T15/06 ,  G06T15/00 ,  G06N3/02

    Abstract: Ray tracing hardware accelerators supporting multiple specifiers for controlling the traversal of a ray tracing acceleration data structure are disclosed. For example, traversal efficiency and complex ray tracing effects can be achieved by specifying traversals through such data structures using both programmable ray operations and explicit node masking. The explicit node masking utilizes dedicated fields in the ray and in nodes of the acceleration data structure to control traversals. Ray operations, however, are programmable per ray using opcodes and additional parameters to control traversals. Traversal efficiency is improved by enabling more aggressive culling of parts of the data structure based on the combination of explicit node masking and programmable ray operations. More complex ray tracing effects are enabled by providing for dynamic selection of nodes based on individual ray characteristics.

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