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1.发明申请公开(公告)号：US20200051318A1
公开(公告)日：2020-02-13
申请号：US16101232
申请日：2018-08-10
申请人： NVIDIA Corporation
发明人： Greg MUTHLER , Ronald Charles BABICH, JR. , William Parsons NEWHALL, JR. , Peter NELSON , James ROBERTSON , John BURGESS
摘要： In a ray tracer, to prevent any long-running query from hanging the graphics processing unit, a traversal coprocessor provides a preemption mechanism that will allow rays to stop processing or time out early. The example non-limiting implementations described herein provide such a preemption mechanism, including a forward progress guarantee, and additional programmable timeout options that can be time or cycle based. Those programmable options provide a means for quality of service timing guarantees for applications such as virtual reality (VR) that have strict timing requirements.
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2.发明申请公开(公告)号：US20200160588A1
公开(公告)日：2020-05-21
申请号：US16749089
申请日：2020-01-22
申请人： NVIDIA Corporation
发明人： Greg MUTHLER , Tero KARRAS , Samuli LAINE , William Parsons NEWHALL, JR. , Ronald Charles BABICH, JR. , John BURGESS , Ignacio LLAMAS
IPC分类号： G06T15/06
摘要： A hardware-based traversal coprocessor provides acceleration of tree traversal operations searching for intersections between primitives represented in a tree data structure and a ray. The primitives may include opaque and alpha triangles used in generating a virtual scene. The hardware-based traversal coprocessor is configured to determine primitives intersected by the ray, and return intersection information to a streaming multiprocessor for further processing. The hardware-based traversal coprocessor is configured to omit reporting of one or more primitives the ray is determined to intersect. The omitted primitives include primitives which are provably capable of being omitted without a functional impact on visualizing the virtual scene.
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公开(公告)号：US20200051315A1
公开(公告)日：2020-02-13
申请号：US16101180
申请日：2018-08-10
申请人： NVIDIA Corporation
发明人： Samuli Laine , Timo AILA , Tero KARRAS , Gregory MUTHLER , William Parsons NEWHALL, JR. , Ronald Charles BABICH, JR. , Craig KOLB , Ignacio LLAMAS
摘要： Methods and systems are described in some examples for changing the traversal of an acceleration data structure in a highly dynamic query-specific manner, with each query specifying test parameters, a test opcode and a mapping of test results to actions. In an example ray tracing implementation, traversal of a bounding volume hierarchy by a ray is performed with the default behavior of the traversal being changed in accordance with results of a test performed using the test opcode and test parameters specified in the ray data structure and another test parameter specified in a node of the bounding volume hierarchy. In an example implementation a traversal coprocessor is configured to perform the traversal of the bounding volume hierarchy.
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公开(公告)号：US20220027280A1
公开(公告)日：2022-01-27
申请号：US17483133
申请日：2021-09-23
申请人： NVIDIA Corporation
发明人： Greg MUTHLER , Timo AILA , Tero KARRAS , Samuli LAINE , William Parsons NEWHALL, JR. , Ronald Charles BABICH, JR. , John BURGESS , Ignacio LLAMAS
IPC分类号： G06F12/0875 , G06T15/06 , G06F16/901
摘要： In a ray tracer, a cache for streaming workloads groups ray requests for coherent successive bounding volume hierarchy traversal operations by sending common data down an attached data path to all ray requests in the group at the same time or about the same time. Grouping the requests provides good performance with a smaller number of cache lines.
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公开(公告)号：US20200051316A1
公开(公告)日：2020-02-13
申请号：US16101196
申请日：2018-08-10
申请人： NVIDIA Corporation
发明人： Samuli LAINE , Tero KARRAS , Greg MUTHLER , William Parsons NEWHALL, JR. , Ronald Charles BABICH , Ignacio LLAMAS , John BURGESS
摘要： A hardware-based traversal coprocessor provides acceleration of tree traversal operations searching for intersections between primitives represented in a tree data structure and a ray. The primitives may include opaque and alpha triangles used in generating a virtual scene. The hardware-based traversal coprocessor is configured to determine primitives intersected by the ray, and return intersection information to a streaming multiprocessor for further processing. The hardware-based traversal coprocessor is configured to provide a deterministic result of intersected triangles regardless of the order that the memory subsystem returns triangle range blocks for processing, while opportunistically eliminating alpha intersections that lie further along the length of the ray than closer opaque intersections.
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公开(公告)号：US20240211255A1
公开(公告)日：2024-06-27
申请号：US18596106
申请日：2024-03-05
申请人： NVIDIA Corporation
发明人： Ronald Charles BABICH, JR. , John BURGESS , Jack CHOQUETTE , Tero KARRAS , Samuli LAINE , Ignacio LLAMAS , Gregory MUTHLER , William Parsons NEWHALL, JR.
CPC分类号： G06F9/3004 , G06F9/3877 , G06F9/4843 , G06F15/163 , G06T1/20 , G06T1/60 , G06T2200/28
摘要： Systems and methods for an efficient and robust multiprocessor-coprocessor interface that may be used between a streaming multiprocessor and an acceleration coprocessor in a GPU are provided. According to an example implementation, in order to perform an acceleration of a particular operation using the coprocessor, the multiprocessor: issues a series of write instructions to write input data for the operation into coprocessor-accessible storage locations, issues an operation instruction to cause the coprocessor to execute the particular operation; and then issues a series of read instructions to read result data of the operation from coprocessor-accessible storage locations to multiprocessor-accessible storage locations.
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7.发明公开公开(公告)号：US20230237729A1
公开(公告)日：2023-07-27
申请号：US18129334
申请日：2023-03-31
申请人： NVIDIA Corporation
发明人： Greg MUTHLER , Tero KARRAS , Samuli LAINE , William Parsons NEWHALL, JR. , Ronald Charles BABICH, JR. , John BURGESS , Ignacio LLAMAS
IPC分类号： G06T15/06
CPC分类号： G06T15/06
摘要： A hardware-based traversal coprocessor provides acceleration of tree traversal operations searching for intersections between primitives represented in a tree data structure and a ray. The primitives may include opaque and alpha triangles used in generating a virtual scene. The hardware-based traversal coprocessor is configured to determine primitives intersected by the ray, and return intersection information to a streaming multiprocessor for further processing. The hardware-based traversal coprocessor is configured to omit reporting of one or more primitives the ray is determined to intersect. The omitted primitives include primitives which are provably capable of being omitted without a functional impact on visualizing the virtual scene.
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8.发明申请公开(公告)号：US20200051317A1
公开(公告)日：2020-02-13
申请号：US16101206
申请日：2018-08-10
申请人： NVIDIA Corporation
发明人： Greg MUTHLER , Ronald Charles BABICH, JR. , William Parsons NEWHALL, JR. , Peter NELSON , Jim ROBERTSON , John BURGESS
摘要： In a ray tracer, to prevent any long-running query from hanging the graphics processing unit, a traversal coprocessor provides a preemption mechanism that will allow rays to stop processing or time out early. The example non-limiting implementations described herein provide such a preemption mechanism, including a forward progress guarantee, and additional programmable timeout options that can be time or cycle based. Those programmable options provide a means for quality of service timing guarantees for applications such as virtual reality (VR) that have strict timing requirements.
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公开(公告)号：US20200050451A1
公开(公告)日：2020-02-13
申请号：US16101247
申请日：2018-08-10
申请人： NVIDIA Corporation
发明人： Ronald Babich , John BURGESS , Jack CHOQUETTE , Tero KARRAS , Samuli LAINE , Ignacio LLAMAS , Gregory MUTHLER , William Parsons NEWHALL, JR.
摘要： Systems and methods for an efficient and robust multiprocessor-coprocessor interface that may be used between a streaming multiprocessor and an acceleration coprocessor in a GPU are provided. According to an example implementation, in order to perform an acceleration of a particular operation using the coprocessor, the multiprocessor: issues a series of write instructions to write input data for the operation into coprocessor-accessible storage locations, issues an operation instruction to cause the coprocessor to execute the particular operation; and then issues a series of read instructions to read result data of the operation from coprocessor-accessible storage locations to multiprocessor-accessible storage locations.
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