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公开(公告)号：US20240013471A1
公开(公告)日：2024-01-11
申请号：US18471651
申请日：2023-09-21
Applicant: NVIDIA CORPORATION
Inventor： Samuli LAINE , Timo AILA , Tero KARRAS , Gregory MUTHLER , William P. NEWHALL, JR. , Ronald C. BABICH, JR. , Craig KOLB , Ignacio LLAMAS , John BURGESS
CPC classification number: G06T15/06 , G06T15/005 , G06T17/005
Abstract: Methods and systems are described in some examples for changing the traversal of an acceleration data structure in a highly dynamic query-specific manner, with each query specifying test parameters, a test opcode and a mapping of test results to actions. In an example ray tracing implementation, traversal of a bounding volume hierarchy by a ray is performed with the default behavior of the traversal being changed in accordance with results of a test performed using the test opcode and test parameters specified in the ray data structure and another test parameter specified in a node of the bounding volume hierarchy. In an example implementation a traversal coprocessor is configured to perform the traversal of the bounding volume hierarchy.
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公开(公告)号：US20220027280A1
公开(公告)日：2022-01-27
申请号：US17483133
申请日：2021-09-23
Applicant: NVIDIA Corporation
Inventor： Greg MUTHLER , Timo AILA , Tero KARRAS , Samuli LAINE , William Parsons NEWHALL, JR. , Ronald Charles BABICH, JR. , John BURGESS , Ignacio LLAMAS
IPC: G06F12/0875 , G06T15/06 , G06F16/901
Abstract: In a ray tracer, a cache for streaming workloads groups ray requests for coherent successive bounding volume hierarchy traversal operations by sending common data down an attached data path to all ray requests in the group at the same time or about the same time. Grouping the requests provides good performance with a smaller number of cache lines.
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公开(公告)号：US20220020202A1
公开(公告)日：2022-01-20
申请号：US17490024
申请日：2021-09-30
Applicant: NVIDIA Corporation
Inventor： Samuli LAINE , Tero KARRAS , Greg MUTHLER , William Parsons NEWHALL , Ronald Charles BABICH , Ignacio LLAMAS , John BURGESS
Abstract: A hardware-based traversal coprocessor provides acceleration of tree traversal operations searching for intersections between primitives represented in a tree data structure and a ray. The primitives may include opaque and alpha triangles used in generating a virtual scene. The hardware-based traversal coprocessor is configured to determine primitives intersected by the ray, and return intersection information to a streaming multiprocessor for further processing. The hardware-based traversal coprocessor is configured to provide a deterministic result of intersected triangles regardless of the order that the memory subsystem returns triangle range blocks for processing, while opportunistically eliminating alpha intersections that lie further along the length of the ray than closer opaque intersections.
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公开(公告)号：US20200051316A1
公开(公告)日：2020-02-13
申请号：US16101196
申请日：2018-08-10
Applicant: NVIDIA Corporation
Inventor： Samuli LAINE , Tero KARRAS , Greg MUTHLER , William Parsons NEWHALL, JR. , Ronald Charles BABICH , Ignacio LLAMAS , John BURGESS
Abstract: A hardware-based traversal coprocessor provides acceleration of tree traversal operations searching for intersections between primitives represented in a tree data structure and a ray. The primitives may include opaque and alpha triangles used in generating a virtual scene. The hardware-based traversal coprocessor is configured to determine primitives intersected by the ray, and return intersection information to a streaming multiprocessor for further processing. The hardware-based traversal coprocessor is configured to provide a deterministic result of intersected triangles regardless of the order that the memory subsystem returns triangle range blocks for processing, while opportunistically eliminating alpha intersections that lie further along the length of the ray than closer opaque intersections.
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公开(公告)号：US20230410410A1
公开(公告)日：2023-12-21
申请号：US18239876
申请日：2023-08-30
Applicant: NVIDIA Corporation
Inventor： Samuli LAINE , Tero KARRAS , Greg MUTHLER , William Parsons Newhall, JR. , Ronald Charles BABACH, JR. , Ignacio LLAMAS , John BURGESS
CPC classification number: G06T15/06 , G06T1/20 , G06T15/005 , G06T2210/21
Abstract: A hardware-based traversal coprocessor provides acceleration of tree traversal operations searching for intersections between primitives represented in a tree data structure and a ray. The primitives may include opaque and alpha triangles used in generating a virtual scene. The hardware-based traversal coprocessor is configured to determine primitives intersected by the ray, and return intersection information to a streaming multiprocessor for further processing. The hardware-based traversal coprocessor is configured to provide a deterministic result of intersected triangles regardless of the order that the memory subsystem returns triangle range blocks for processing, while opportunistically eliminating alpha intersections that lie further along the length of the ray than closer opaque intersections.
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Patent Agency Ranking
6.发明申请公开(公告)号：US20200160588A1
公开(公告)日：2020-05-21
申请号：US16749089
申请日：2020-01-22
Applicant: NVIDIA Corporation
Inventor： Greg MUTHLER , Tero KARRAS , Samuli LAINE , William Parsons NEWHALL, JR. , Ronald Charles BABICH, JR. , John BURGESS , Ignacio LLAMAS
IPC: G06T15/06
Abstract: A hardware-based traversal coprocessor provides acceleration of tree traversal operations searching for intersections between primitives represented in a tree data structure and a ray. The primitives may include opaque and alpha triangles used in generating a virtual scene. The hardware-based traversal coprocessor is configured to determine primitives intersected by the ray, and return intersection information to a streaming multiprocessor for further processing. The hardware-based traversal coprocessor is configured to omit reporting of one or more primitives the ray is determined to intersect. The omitted primitives include primitives which are provably capable of being omitted without a functional impact on visualizing the virtual scene.
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公开(公告)号：US20200051315A1
公开(公告)日：2020-02-13
申请号：US16101180
申请日：2018-08-10
Applicant: NVIDIA Corporation
Inventor： Samuli Laine , Timo AILA , Tero KARRAS , Gregory MUTHLER , William Parsons NEWHALL, JR. , Ronald Charles BABICH, JR. , Craig KOLB , Ignacio LLAMAS
Abstract: Methods and systems are described in some examples for changing the traversal of an acceleration data structure in a highly dynamic query-specific manner, with each query specifying test parameters, a test opcode and a mapping of test results to actions. In an example ray tracing implementation, traversal of a bounding volume hierarchy by a ray is performed with the default behavior of the traversal being changed in accordance with results of a test performed using the test opcode and test parameters specified in the ray data structure and another test parameter specified in a node of the bounding volume hierarchy. In an example implementation a traversal coprocessor is configured to perform the traversal of the bounding volume hierarchy.
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公开(公告)号：US20200050550A1
公开(公告)日：2020-02-13
申请号：US16101109
申请日：2018-08-10
Applicant: NVIDIA Corporation
Inventor： Greg MUTHLER , Timo AILA , Tero KARRAS , Samuli LAINE , William Parsons NEWHALL , Ronald Charles BABICH , John BURGESS , Ignacio LLAMAS
IPC: G06F12/0875 , G06T15/06 , G06F17/30
Abstract: In a ray tracer, a cache for streaming workloads groups ray requests for coherent successive bounding volume hierarchy traversal operations by sending common data down an attached data path to all ray requests in the group at the same time or about the same time. Grouping the requests provides good performance with a smaller number of cache lines.
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公开(公告)号：US20250104332A1
公开(公告)日：2025-03-27
申请号：US18971672
申请日：2024-12-06
Applicant: NVIDIA CORPORATION
Inventor： Samuli LAINE , Timo AILA , Tero KARRAS , Gregory MUTHLER , William P. NEWHALL, JR. , Ronald C BABICH, JR. , Craig KOLB , Ignacio LLAMAS , John BURGESS
Abstract: Methods and systems are described in some examples for changing the traversal of an acceleration data structure in a highly dynamic query-specific manner, with each query specifying test parameters, a test opcode and a mapping of test results to actions. In an example ray tracing implementation, traversal of a bounding volume hierarchy by a ray is performed with the default behavior of the traversal being changed in accordance with results of a test performed using the test opcode and test parameters specified in the ray data structure and another test parameter specified in a node of the bounding volume hierarchy. In an example implementation a traversal coprocessor is configured to perform the traversal of the bounding volume hierarchy.
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公开(公告)号：US20250004947A1
公开(公告)日：2025-01-02
申请号：US18882707
申请日：2024-09-11
Applicant: NVIDIA Corporation
Inventor： Gregory A. MUTHLER , Timo AILA , Tero KARRAS , Samuli LAINE , William Parsons NEWHALL, JR. , Ronald Charles BABICH, JR. , John BURGESS , Ignacio LLAMAS
IPC: G06F12/0875 , G06F16/901 , G06T15/06
Abstract: In a ray tracer, a cache for streaming workloads groups ray requests for coherent successive bounding volume hierarchy traversal operations by sending common data down an attached data path to all ray requests in the group at the same time or about the same time. Grouping the requests provides good performance with a smaller number of cache lines.
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