公开(公告)号：US07376002B2

公开(公告)日：2008-05-20

申请号：US11384242

申请日：2006-03-21

申请人： Koji Nii

发明人： Koji Nii

IPC分类号： G11C11/00

CPC分类号： G11C11/412 ,  G11C8/16 ,  H01L27/105 ,  H01L27/11 ,  H01L27/1104

摘要： In a multiport SRAM memory cell of the present invention, an access transistor of a first port is disposed in a p-type well, and an access transistor of a second port is disposed in a p-type well. The gates of all of transistors disposed in a memory cell extend in the same direction. With the configuration, a semiconductor memory device having a low-power consumption type SRAM memory cell with an increased margin of variations in manufacturing, by which a bit line can be shortened in a multiport SRAM memory cell or an associative memory, can be obtained.

摘要翻译： 在本发明的多端口SRAM存储单元中，第一端口的存取晶体管设置在p型阱中，第二端口的存取晶体管设置在p型阱中。 设置在存储单元中的所有晶体管的栅极沿相同的方向延伸。 通过该配置，可以获得具有在多端口SRAM存储单元或关联存储器中可以缩短位线的制造中的变化幅度增加的低功耗型SRAM存储单元的半导体存储器件。

公开(公告)号：US07170812B2

公开(公告)日：2007-01-30

申请号：US11304817

申请日：2005-12-16

申请人： Koji Nii

发明人： Koji Nii

IPC分类号： G11C5/14

CPC分类号： G11C11/417

摘要： The input data at address 0 is “00000000”, including many “0”s. The data at address 0 is inverted to “11111111”. At the same time, flag information “1” indicative of inversion is written into the flag bit of the same address 0. The input data at address 3 also includes many “0”s. Therefore, the data of address 3 is inverted, and flag information “1” is written. The input data at addresses 1 and 2 includes more “1”s than “0”s. Therefore, the data is not inverted, and flag information “0” is written. With regards to the written data, only the data at an address whose flag signal is “1” is inverted again in a reading mode to be eventually read out as a data output signal.

摘要翻译： 地址0的输入数据为“00000000”，包括许多“0”。 地址0的数据被反转为“11111111”。 同时，将表示反转的标志信息“1”写入相同地址0的标志位。 地址3处的输入数据也包括许多“0”。 因此，地址3的数据被反转，并且写入标志信息“1”。 地址1和2的输入数据比“0”更多的“1”。 因此，数据不反转，写入标志信息“0”。 关于写入数据，仅在标志信号为“1”的地址处的数据在读取模式下再次反相，最终作为数据输出信号被读出。

公开(公告)号：US20060274571A1

公开(公告)日：2006-12-07

申请号：US11504077

申请日：2006-08-15

申请人： Noriaki Maeda ,  Yoshihiro Shinozaki ,  Masanao Yamaoka ,  Yasuhisa Shimazaki ,  Masanori Isoda ,  Koji Nii

发明人： Noriaki Maeda ,  Yoshihiro Shinozaki ,  Masanao Yamaoka ,  Yasuhisa Shimazaki ,  Masanori Isoda ,  Koji Nii

IPC分类号： G11C11/00

CPC分类号： G11C11/412 ,  G11C5/063 ,  G11C5/14 ,  G11C11/419 ,  H01L27/11 ,  H01L27/1104

摘要： The invention provides a semiconductor integrated circuit device provided with an SRAM that satisfies the requirements for both the SNM and the write margin with a low supply voltage. The semiconductor integrated circuit device include: multiple static memory cells provided in correspondence with multiple word lines and multiple complimentary bit lines; multiple memory cell power supply lines that each supply an operational voltage to each of the multiple memory cells connected to the multiple complimentary bit lines each; multiple power supply circuits comprised of resistive units that each supply a power supply voltage to the memory cell power supply lines each; and a pre-charge circuit that supplies a pre-charge voltage corresponding to the power supply voltage to the complimentary bit lines, wherein the memory cell power supply lines are made to have coupling capacitances to thereby transmit a write signal on corresponding complimentary bit lines.

公开(公告)号：US20060092746A1

公开(公告)日：2006-05-04

申请号：US11304817

申请日：2005-12-16

申请人： Koji Nii

发明人： Koji Nii

IPC分类号： G11C5/14

CPC分类号： G11C11/417

摘要： The input data at address 0 is “00000000”, including many “0”s. The data at address 0 is inverted to “11111111”. At the same time, flag information “1” indicative of inversion is written into the flag bit of the same address 0. The input data at address 3 also includes many “0”s. Therefore, the data of address 3 is inverted, and flag information “1” is written. The input data at addresses 1 and 2 includes more “1”s than “0”s. Therefore, the data is not inverted, and flag information “0” is written. With regards to the written data, only the data at an address whose flag signal is “1” is inverted again in a reading mode to be eventually read out as a data output signal.

摘要翻译： 地址0的输入数据为“00000000”，包括许多“0”。 地址0的数据被反转为“11111111”。 同时，将表示反转的标志信息“1”写入相同地址0的标志位。 地址3处的输入数据也包括许多“0”。 因此，地址3的数据被反转，并且写入标志信息“1”。 地址1和2的输入数据比“0”更多的“1”。 因此，数据不反转，写入标志信息“0”。 关于写入数据，仅在标志信号为“1”的地址处的数据在读取模式下再次反相，最终作为数据输出信号被读出。

公开(公告)号：US07035135B2

公开(公告)日：2006-04-25

申请号：US11207938

申请日：2005-08-22

申请人： Koji Nii

发明人： Koji Nii

IPC分类号： G11C11/00

CPC分类号： G11C11/412 ,  G11C8/16 ,  H01L27/105 ,  H01L27/11 ,  H01L27/1104

摘要： In a multiport SRAM memory cell of the present invention, an access transistor of a first port is disposed in a p-type well, and an access transistor of a second port is disposed in a p-type well. The gates of all of transistors disposed in a memory cell extend in the same direction. With the configuration, a semiconductor memory device having a low-power consumption type SRAM memory cell with an increased margin of variations in manufacturing, by which a bit line can be shortened in a multiport SRAM memory cell or an associative memory, can be obtained.

公开(公告)号：US20060044866A1

公开(公告)日：2006-03-02

申请号：US11211682

申请日：2005-08-26

申请人： Yasumasa Tsukamoto ,  Koji Nii

发明人： Yasumasa Tsukamoto ,  Koji Nii

IPC分类号： G11C11/00

CPC分类号： G11C11/412 ,  G11C11/413

摘要： The invention provides a semiconductor device capable of reducing wasteful power consumption. The semiconductor device of the invention does not require a refresh operation, and includes memory circuits for storing data, arranged in a matrix form, first signal lines for reading data from the memory circuits, second signal lines for transferring a signal that controls connection between the memory circuits and the first signal lines, a sense amplifier circuit for reading and determining data by detecting a potential change or a current change in the first signal lines, and a mitigating means for mitigating the potential change or the current change in the first signal lines during a period in which the sense amplifier circuit is being activated.

摘要翻译： 本发明提供能够减少浪费的功耗的半导体器件。 本发明的半导体器件不需要刷新操作，并且包括用于存储以矩阵形式布置的数据的存储器电路，用于从存储器电路读取数据的第一信号线，用于传送控制在存储器电路之间的连接的信号的第二信号线 存储器电路和第一信号线，用于通过检测第一信号线中的电位变化或电流变化来读取和确定数据的读出放大器电路，以及用于减轻第一信号线中的电位变化或电流变化的减轻装置 在读出放大器电路被激活的时间段内。

公开(公告)号：US06917560B2

公开(公告)日：2005-07-12

申请号：US10691707

申请日：2003-10-24

申请人： Koji Nii

发明人： Koji Nii

IPC分类号： G11C11/41 ,  G11C8/16 ,  H01L21/8244 ,  H01L27/108 ,  H01L27/11 ,  G11C8/00

CPC分类号： G11C5/063 ,  G11C8/16

摘要： A semiconductor memory device having a multiport memory includes a plurality of memory cells MC arranged in columns and rows, a plurality of first word lines WLA0-WLAn connected to a first port 13a, and a plurality of second word lines WLB0-WLBn connected to a second port 13b. Each of a plurality of first word lines WLA0-WLAn and each of a plurality of second word lines WLB0-WLBn are arranged alternately in a planar layout. A semiconductor memory device is thus obtained that allows a coupling noise between interconnections to be reduced without an increase in memory cell area.

摘要翻译： 具有多端口存储器的半导体存储器件包括以列和行布置的多个存储单元MC，连接到第一端口13a的多个第一字线WLA 0 -WLAn以及多个第二字线WLB 0 -WLBn 连接到第二端口13b。 多个第一字线WLA 0 -WLAn和多个第二字线WLB 0 -WLBn中的每一个交替地布置在平面布局中。 因此获得了允许互连之间的耦合噪声减小而不增加存储单元面积的半导体存储器件。

公开(公告)号：US06815839B2

公开(公告)日：2004-11-09

申请号：US10668330

申请日：2003-09-24

申请人： Koji Nii ,  Motoshige Igarashi

发明人： Koji Nii ,  Motoshige Igarashi

IPC分类号： H01L2711

CPC分类号： G11C11/412 ,  Y10S257/903 ,  Y10S257/904

摘要： The semiconductor memory device includes two PMOS transistors that make the SRAM memory cell. The gate insulating films of these PMOS transistors are formed using a material that has a high permittivity. As a result, the capacitance of memory nodes is increased, and the probability of soft errors is lowered.

摘要翻译： 半导体存储器件包括制造SRAM存储单元的两个PMOS晶体管。 这些PMOS晶体管的栅极绝缘膜使用具有高介电常数的材料形成。 结果，存储器节点的电容增加，并且软错误的概率降低。

公开(公告)号：USRE35591E

公开(公告)日：1997-08-19

申请号：US679391

申请日：1996-07-10

申请人： Koji Nii ,  Hideshi Maeno

发明人： Koji Nii ,  Hideshi Maeno

IPC分类号： H01L27/118 ,  G11C11/412 ,  G11C11/419 ,  H01L21/82 ,  H01L27/10 ,  G11C11/40

CPC分类号： G11C11/412 ,  G11C11/419

摘要： Memory cells having a stable write operation are formed in an array on a CMOS gate array semiconductor substrate. Each memory cell includes mutually adjacent transistors from a first pair of complementary conductivity type MOS transistor rows. These transistors are used to form a flip-flop and first and second access gates. The memory cell further includes mutually adjacent MOS transistors from a second pair of complementary conductivity type MOS transistor rows. These transistors are used to form an inverter and a third access gate connected to the output of the inverter. The input of the inverter is connected to one end of the flip-flop. The inputs of the first and second access gates are connected to bit lines through which complementary data signals are applied. The gates of the first and second access gate transistors are connected to a write word line. The third access gate is connected to a readout signal providing bit line, and the gate of the third access gate MOS transistor is connected to a read word line.

摘要翻译： 具有稳定写入操作的存储单元以CMOS阵列半导体衬底上的阵列形成。 每个存储单元包括来自第一对互补导电型MOS晶体管列的相互相邻的晶体管。 这些晶体管用于形成触发器和第一和第二存取门。 存储单元还包括来自第二对互补导电型MOS晶体管列的相互相邻的MOS晶体管。 这些晶体管用于形成逆变器和连接到逆变器的输出的第三存取栅。 反相器的输入端连接到触发器的一端。 第一和第二访问门的输入连接到施加了互补数据信号的位线。 第一和第二存取栅极晶体管的栅极连接到写入字线。 第三存取栅极连接到提供位线的读出信号，第三存取门MOS晶体管的栅极连接到读取字线。

公开(公告)号：US5535159A

公开(公告)日：1996-07-09

申请号：US383860

申请日：1995-02-06

申请人： Koji Nii

发明人： Koji Nii

IPC分类号： G11C11/41 ,  G11C8/16 ,  H01L27/118 ,  G11C7/00

CPC分类号： H01L27/11807 ,  G11C8/16

摘要： In order to improve ability for driving the potential of a read bit line (192) to a high level, an output terminal (201b) of a memory circuit (21) and a read word line (182) are connected input terminals (204, 205) of a NAND gate (15) respectively. A gate of a transistor (123) is connected to an output terminal (203) of the NAND gate (15) and its source is connected to a power supply line (111) to be supplied with a VDD potential, while its drain is connected to the read bit line (192). MOS transistors (133, 134) are connected in series between the bit line (192) and a grounding conductor (112). Gates of the transistors (133, 134) are connected to the output terminal (203) and the input terminal (205) of the NAND gate (15) respectively. Thus, a time for converting the output terminal from a low level to a high level is reduced, whereby an access time can be reduced. Other embodiments of the above-described invention include different logic technologies used to construct the memory circuit (172).

摘要翻译： 为了提高将读位线（192）的电位驱动到高电平的能力，存储电路（21）和读字线（182）的输出端（201b）是连接的输入端（204， 205）。 晶体管（123）的栅极连接到NAND门（15）的输出端子（203），其源极连接到供电线（111），以提供VDD电位，而其漏极连接 到读位线（192）。 MOS晶体管（133,134）串联连接在位线（192）和接地导体（112）之间。 晶体管（133,134）的栅极分别连接到NAND门（15）的输出端子（203）和输入端子（205）。 因此，将输出端子从低电平转换为高电平的时间减少，从而可以减少访问时间。 上述发明的其它实施例包括用于构造存储电路（172）的不同逻辑技术。