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    Semiconductor device and manufacturing method of the same
    32.
    发明授权
    Semiconductor device and manufacturing method of the same 失效
    半导体器件及其制造方法相同

    公开(公告)号：US07842973B2

    公开(公告)日：2010-11-30

    申请号：US11485287

    申请日：2006-07-13

    申请人： Makoto Miura ,  Katsuyoshi Washio ,  Hiromi Shimamoto

    发明人： Makoto Miura ,  Katsuyoshi Washio ,  Hiromi Shimamoto

    IPC分类号： H01L29/737 ,  H01L21/331

    CPC分类号： H01L29/7378 ,  Y10S438/936

    摘要： A semiconductor device capable of avoiding generation of a barrier in a conduction band while maintaining high withstanding voltage and enabling high speed transistor operation at high current in a double hetero bipolar transistor, as well as a manufacturing method thereof, wherein a portion of the base and the collector is formed of a material with a forbidden band width narrower than that of a semiconductor substrate, a region where the forbidden band increases stepwise and continuously from the emitter side to the collector side is disposed in the inside of the base and the forbidden band width at the base-collector interface is designed so as to be larger than the minimum forbidden band width in the base, whereby the forbidden band width at the base layer edge on the collector side can be made closer to the forbidden band width of the semiconductor substrate than usual while sufficiently maintaining the hetero effect near the emitter-base thereby capable of decreasing the height of the energy barrier generated upon increase of the collector current and enabling satisfactory transistor operation at high current.

    摘要翻译： 一种半导体器件及其制造方法，其能够在保持高耐受电压的同时避免在导带中产生阻挡层并能够在高电流下进行高速晶体管的操作，以及其制造方法，其中， 集电体由禁带宽度窄于半导体衬底的材料形成，禁带从发射极侧向集电极侧逐步且连续地增加的区域设置在基体的内部，禁带 在基极集电体界面的宽度被设计为大于基极中的最小禁带宽度，由此集电极侧的基底边缘处的禁带宽度可以更接近半导体的禁带宽度 衬底，同时充分保持发射极基极附近的杂质效应，从而能够降低高度 在集电极电流增加时产生能量势垒，并且能够在高电流下令人满意的晶体管工作。

    Semiconductor device and manufacturing method for the same
    33.
    发明授权
    Semiconductor device and manufacturing method for the same 失效
    半导体器件及其制造方法相同

    公开(公告)号：US07071500B2

    公开(公告)日：2006-07-04

    申请号：US10866673

    申请日：2004-06-15

    申请人： Makoto Miura ,  Katsuyoshi Washio ,  Hiromi Shimamoto

    发明人： Makoto Miura ,  Katsuyoshi Washio ,  Hiromi Shimamoto

    IPC分类号： H01L31/072

    CPC分类号： H01L29/66287 ,  H01L29/0821 ,  H01L29/41708 ,  H01L29/732

    摘要： A bipolar semiconductor device including a collector layer covered at a portion of an outer periphery thereof with an insulating film and having a shape extending in an upper direction and a horizontal direction, with a gap being formed between the collector layer and the insulating film, and further including a base layer and an emitter layer disposed over the collector layer, and a manufacturing method of the semiconductor device. Since the collector layer has a shape extending in a portion thereof in the upward direction and the horizontal direction, an external collector region can be deleted, and both the parasitic capacitance and the collector capacitance in the intrinsic portion attributable to the collector can be decreased and, accordingly, a bipolar transistor capable of high speed operation at a reduced consumption power can be constituted.

    摘要翻译： 一种双极半导体器件，包括在其外周的一部分上覆盖有绝缘膜并且具有在上方向和水平方向上延伸的形状的集电极层，在集电层和绝缘膜之间形成间隙，以及 还包括设置在集电极层上的基极层和发射极层，以及半导体器件的制造方法。 由于集电体层的一部分在上下方向和水平方向上延伸，所以可以消除外部集电极区域，能够减少归因于集电体的本征部分的寄生电容和集电极电容， 因此，可以构成能够以降低的消耗功率进行高速运转的双极型晶体管。

    Bipolar transistor and manufacturing method thereof
    36.
    发明授权
    Bipolar transistor and manufacturing method thereof 失效
    双极晶体管及其制造方法

    公开(公告)号：US06521974B1

    公开(公告)日：2003-02-18

    申请号：US09689800

    申请日：2000-10-13

    申请人： Katsuya Oda ,  Eiji Ohue ,  Masao Kondo ,  Katsuyoshi Washio ,  Masamichi Tanabe ,  Hiromi Shimamoto

    发明人： Katsuya Oda ,  Eiji Ohue ,  Masao Kondo ,  Katsuyoshi Washio ,  Masamichi Tanabe ,  Hiromi Shimamoto

    IPC分类号： H01L2970

    CPC分类号： H01L29/66287 ,  H01L29/66242 ,  H01L29/732 ,  H01L29/7378

    摘要： A bipolar transistor according to the invention is provided with structure that an intrinsic base made of single crystal Si—Ge and a base leading-out electrode are connected via a link base made of polycrystal Si—Ge by doping at high concentration, further, a part immediately under the intrinsic base has the same conductive type as that of a collector and in a peripheral part, a single crystal Si—Ge layer having the same conductive type as that of a base is provided between the intrinsic base and a collector layer. Hereby, the reduction of the resistance of the link base between the intrinsic base and the base leading-out electrode and the reduction of capacitance between the collector and the base are simultaneously realized, and a self-aligned bipolar transistor wherein capacitance between an emitter and the base and capacitance between the collector and the base are respectively small, power consumption is small and high speed operation is enabled is acquired.

    摘要翻译： 根据本发明的双极晶体管具有以下结构：由单晶Si-Ge构成的本征基极和基极引出电极通过高浓度掺杂的由多晶Si-Ge制成的连接基底连接，此外， 在本征基底之下的部分具有与集电体相同的导电类型，并且在外围部分中，在本征基极和集电极层之间设置具有与基底相同的导电类型的单晶Si-Ge层。 因此，同时实现本征基极与基极引出电极之间的基极的电阻的降低和集电极与基极之间的电容的减小，以及自对准双极晶体管，其中发射极和 集电极和基极之间的基极和电容分别小，功耗小，获得高速运行。

    BICMOS semiconductor integrated circuit device and fabrication process thereof
    37.
    发明授权
    BICMOS semiconductor integrated circuit device and fabrication process thereof 失效
    BICMOS半导体集成电路器件及其制造工艺

    公开(公告)号：US06476450B2

    公开(公告)日：2002-11-05

    申请号：US09808952

    申请日：2001-03-16

    申请人： Masao Kondo ,  Katsuyoshi Washio ,  Eiji Oue ,  Hiromi Shimamoto

    发明人： Masao Kondo ,  Katsuyoshi Washio ,  Eiji Oue ,  Hiromi Shimamoto

    IPC分类号： H01L29732

    CPC分类号： H01L27/0623 ,  H01L21/8249 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Provided is a BiCOMOS semiconductor integrated circuit device which comprises a semiconductor substrate having an insulating layer internally and partially embedded therein and a semiconductor layer deposited on the insulating layer, an insulated gate type transistor formed in the semiconductor layer, a highly-doped collector layer of a bipolar transistor embedded in an insulating-layer-free portion of the semiconductor substrate, and a low-doped collector layer disposed on the highly-doped collector layer of the bipolar transistor, wherein the height level of the lower portion of the low-doped collector layer is below the height level of the lower portion of the insulating layer so as to attain high breakdown voltage and high speed operation of the bipolar transistor.

    摘要翻译： 本发明提供一种BiCOMOS半导体集成电路器件，其包括半导体衬底，该半导体衬底具有内部并部分地嵌入其中的绝缘层和沉积在绝缘层上的半导体层，形成在半导体层中的绝缘栅型晶体管，高度掺杂的集电极层 嵌入在半导体衬底的绝缘层的部分中的双极晶体管，以及设置在双极晶体管的高掺杂集电极层上的低掺杂集电极层，其中低掺杂量的下部的高度电平 集电极层在绝缘层的下部的高度以下，以获得双极晶体管的高击穿电压和高速工作。

    Bipolar transistor
    38.
    发明授权
    Bipolar transistor 失效

    公开(公告)号：US06388307B1

    公开(公告)日：2002-05-14

    申请号：US09376352

    申请日：1999-08-18

    申请人： Masao Kondo ,  Katsuya Oda ,  Katsuyoshi Washio

    发明人： Masao Kondo ,  Katsuya Oda ,  Katsuyoshi Washio

    IPC分类号： H01L2782

    CPC分类号： H01L31/1105

    摘要： A bipolar transistor using a B-doped Si and Ge alloy for a base in which a Ge content in an emitter-base depletion region and in a base-collector depletion region is greater than a Ge content in a base layer. Diffusion of B from the base layer can be suppressed by making the Ge content in the emitter-base depletion region and in a base-collector depletion region on both sides of the base layer greater than the Ge content in the base layer since the diffusion coefficient of B in the SiGe layer is lowered as the Ge contents increases.

    Heterojunction bipolar transistor
    39.
    发明授权
    Heterojunction bipolar transistor 失效
    异质结双极晶体管

    公开(公告)号：US5962880A

    公开(公告)日：1999-10-05

    申请号：US892673

    申请日：1997-07-14

    申请人： Katsuya Oda ,  Eiji Ohue ,  Takahiro Onai ,  Katsuyoshi Washio

    发明人： Katsuya Oda ,  Eiji Ohue ,  Takahiro Onai ,  Katsuyoshi Washio

    IPC分类号： H01L21/331 ,  H01L29/10 ,  H01L29/737

    CPC分类号： H01L29/66242 ,  H01L29/1004 ,  H01L29/7378

    摘要： A self-aligned bipolar transistor which has a small base resistance and small emitter-base and collector-base capacitances and is operable at high speed is disclosed. This bipolar transistor is characterized in that a low concentration collector region made of single crystal Si--Ge is self-alignedly formed between an intrinsic base of single crystal Si--Ge and an intrinsic base, and that an extrinsic base electrode and an intrinsic base are connected only through a doped external base. With this arrangement, an energy barrier is not established at the collector base interface owing to the formation of the low concentration region of single crystal Si--Ge, so that the transit time of the carriers charged from the emitter is shortened. The connection between the intrinsic base and the extrinsic base electrode via the doped external base results in the reduction of the base resistance. In addition, the self-aligned formation of the emitter-base-collector leads to the reduction in capacitance between the emitter and the base and also between the collector and the base. Accordingly, a high-speed bipolar transistor can be realized and thus, circuits using the transistor are operable at high speed.

    摘要翻译： 公开了具有小的基极电阻和小的发射极基极和集电极基极电容并且可高速操作的自对准双极晶体管。 该双极型晶体管的特征在于，由单晶Si-Ge构成的低浓度集电极区域在单晶Si-Ge的本征基极和本征基极之间自对准地形成，而外部基极电极和固有基极为 仅通过掺杂的外部基极连接。 通过这种布置，由于形成单晶Si-Ge的低浓度区域，在集电极基极界面处没有形成能量势垒，从而缩短了从发射极充电的载流子的渡越时间。 通过掺杂的外部基极的本征基极和外部基极之间的连接导致基极电阻的降低。 此外，发射极 - 基极集电体的自对准形成导致发射极和基极之间以及集电极和基极之间的电容减小。 因此，可以实现高速双极晶体管，因此，使用晶体管的电路可以高速工作。