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    Semiconductor device and drive circuit using the semiconductor devices
    1.
    发明授权
    Semiconductor device and drive circuit using the semiconductor devices 失效
    使用半导体器件的半导体器件和驱动电路

    公开(公告)号：US06956255B2

    公开(公告)日：2005-10-18

    申请号：US10289306

    申请日：2002-11-07

    申请人： Eiji Oue ,  Katsuyoshi Washio ,  Masao Kondo ,  Hiromi Shimamoto

    发明人： Eiji Oue ,  Katsuyoshi Washio ,  Masao Kondo ,  Hiromi Shimamoto

    IPC分类号： H01L21/331 ,  H01L21/76 ,  H01L21/822 ,  H01L21/8234 ,  H01L21/8249 ,  H01L23/367 ,  H01L27/04 ,  H01L27/06 ,  H01L29/73 ,  H01L29/732 ,  H01L29/786 ,  H01L29/80 ,  H01L39/112

    CPC分类号： H01L29/7322 ,  H01L21/8249 ,  H01L23/3677 ,  H01L29/7317 ,  H01L2224/82 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/00

    摘要： A high-speed bipolar transistor is provided which is improved in the effect of heat radiation without increasing the substrate capacitance. The heat radiation connection between a base region and a silicon substrate includes a p+ extrinsic base polysilicon electrode and a polysilicon layer buried in an isolation groove with a very thin silicon dioxide side wall. Accordingly, the heat generated at the base is radiated through this path to the silicon substrate. Further, the film thickness of the silicon dioxide on the inner wall of the isolation groove is sufficiently increased compared with previous structures to prevent an increase in the substrate capacitance. Consequently, there can be obtained a bipolar transistor which operates at high speed, and is improved in the effect of heat radiation without increasing the substrate capacitance.

    摘要翻译： 提供了高速双极晶体管，其在不增加衬底电容的情况下改善了散热的效果。 基极区域和硅衬底之间的热辐射连接包括一个非本征基极多晶硅电极和一个埋在具有非常薄的二氧化硅侧壁的隔离槽中的多晶硅层。 因此，在基底处产生的热量通过该路径被辐射到硅衬底。 此外，与以前的结构相比，隔离槽的内壁上的二氧化硅的膜厚度充分增加，以防止衬底电容的增加。 因此，可以获得高速工作的双极晶体管，并且在不增加衬底电容的情况下提高散热的效果。

    BICMOS semiconductor integrated circuit device and fabrication process thereof
    3.
    发明授权
    BICMOS semiconductor integrated circuit device and fabrication process thereof 失效
    BICMOS半导体集成电路器件及其制造工艺

    公开(公告)号：US06815822B2

    公开(公告)日：2004-11-09

    申请号：US10237705

    申请日：2002-09-10

    申请人： Masao Kondo ,  Katsuyoshi Washio ,  Eiji Oue ,  Hiromi Shimamoto

    发明人： Masao Kondo ,  Katsuyoshi Washio ,  Eiji Oue ,  Hiromi Shimamoto

    IPC分类号： H01L2348

    CPC分类号： H01L27/0623 ,  H01L21/8249 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Provided is a BiCOMOS semiconductor integrated circuit device which comprises a semiconductor substrate having an insulating layer internally and partially embedded therein and a semiconductor layer deposited on the insulating layer, an insulated gate type transistor formed in the semiconductor layer, a highly-doped collector layer of a bipolar transistor embedded in an insulating-layer-free portion of the semiconductor substrate, and a low-doped collector layer disposed on the highly-doped collector layer of the bipolar transistor, wherein the height level of the lower portion of the low-doped collector layer is below the height level of the lower portion of the insulating layer so as to attain high breakdown voltage and high speed operation of the bipolar transistor.

    摘要翻译： 本发明提供一种BiCOMOS半导体集成电路器件，其包括半导体衬底，该半导体衬底具有内部并部分地嵌入其中的绝缘层和沉积在绝缘层上的半导体层，形成在半导体层中的绝缘栅型晶体管，高度掺杂的集电极层 嵌入在半导体衬底的绝缘层的部分中的双极晶体管，以及设置在双极晶体管的高掺杂集电极层上的低掺杂集电极层，其中低掺杂量的下部的高度电平 集电极层在绝缘层的下部的高度以下，以获得双极晶体管的高击穿电压和高速工作。

    BICMOS semiconductor integrated circuit device and fabrication process thereof
    7.
    发明授权
    BICMOS semiconductor integrated circuit device and fabrication process thereof 失效
    BICMOS半导体集成电路器件及其制造工艺

    公开(公告)号：US06476450B2

    公开(公告)日：2002-11-05

    申请号：US09808952

    申请日：2001-03-16

    申请人： Masao Kondo ,  Katsuyoshi Washio ,  Eiji Oue ,  Hiromi Shimamoto

    发明人： Masao Kondo ,  Katsuyoshi Washio ,  Eiji Oue ,  Hiromi Shimamoto

    IPC分类号： H01L29732

    CPC分类号： H01L27/0623 ,  H01L21/8249 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Provided is a BiCOMOS semiconductor integrated circuit device which comprises a semiconductor substrate having an insulating layer internally and partially embedded therein and a semiconductor layer deposited on the insulating layer, an insulated gate type transistor formed in the semiconductor layer, a highly-doped collector layer of a bipolar transistor embedded in an insulating-layer-free portion of the semiconductor substrate, and a low-doped collector layer disposed on the highly-doped collector layer of the bipolar transistor, wherein the height level of the lower portion of the low-doped collector layer is below the height level of the lower portion of the insulating layer so as to attain high breakdown voltage and high speed operation of the bipolar transistor.

    摘要翻译： 本发明提供一种BiCOMOS半导体集成电路器件，其包括半导体衬底，该半导体衬底具有内部并部分地嵌入其中的绝缘层和沉积在绝缘层上的半导体层，形成在半导体层中的绝缘栅型晶体管，高度掺杂的集电极层 嵌入在半导体衬底的绝缘层的部分中的双极晶体管，以及设置在双极晶体管的高掺杂集电极层上的低掺杂集电极层，其中低掺杂量的下部的高度电平 集电极层在绝缘层的下部的高度以下，以获得双极晶体管的高击穿电压和高速工作。

    Semiconductor device and method for manufacturing the same
    8.
    发明申请
    Semiconductor device and method for manufacturing the same 失效
    半导体装置及其制造方法

    公开(公告)号：US20050001238A1

    公开(公告)日：2005-01-06

    申请号：US10855378

    申请日：2004-05-28

    申请人： Eiji Oue ,  Katsuyoshi Washio ,  Hiromi Shimamoto ,  Katsuya Oda ,  Makoto Miura

    发明人： Eiji Oue ,  Katsuyoshi Washio ,  Hiromi Shimamoto ,  Katsuya Oda ,  Makoto Miura

    IPC分类号： H01L21/331 ,  H01L29/732 ,  H01L29/737 ,  H01L31/0328

    CPC分类号： H01L29/66287 ,  H01L29/7322

    摘要： A bipolar transistor is provided in which both the base resistance and the base-collector capacitance are reduced and which is capable of operating at a high cutoff frequency. The semiconductor device is structured so that the emitter and extrinsic base are separated from each other by an insulator sidewall and the bottom faces of the insulator sidewall, and the emitter are approximately on the same plane. The extrinsic base electrode and the collector region are separated from each other by an insulator.

    摘要翻译： 提供双极晶体管，其中基极电阻和基极集电极电容都减小，并且能够以高截止频率工作。 半导体器件被构造成使得发射极和非本征基极通过绝缘体侧壁和绝缘体侧壁的底面彼此分离，并且发射极大致在同一平面上。 外部基极和集电极区域通过绝缘体彼此分离。

    Semiconductor device with reduced base resistance
    9.
    发明授权
    Semiconductor device with reduced base resistance 失效
    具有降低基极电阻的半导体器件

    公开(公告)号：US07521734B2

    公开(公告)日：2009-04-21

    申请号：US10855378

    申请日：2004-05-28

    申请人： Eiji Oue ,  Katsuyoshi Washio ,  Hiromi Shimamoto ,  Katsuya Oda ,  Makoto Miura

    发明人： Eiji Oue ,  Katsuyoshi Washio ,  Hiromi Shimamoto ,  Katsuya Oda ,  Makoto Miura

    IPC分类号： H01L31/0328 ,  H01L31/0336 ,  H01L31/072 ,  H01L31/109

    CPC分类号： H01L29/66287 ,  H01L29/7322

    摘要： A bipolar transistor is provided in which both the base resistance and the base-collector capacitance are reduced and which is capable of operating at a high cutoff frequency. The semiconductor device is structured so that the emitter and extrinsic base are separated from each other by an insulator sidewall and the bottom faces of the insulator sidewall, and the emitter are approximately on the same plane. The extrinsic base electrode and the collector region are separated from each other by an insulator.

    摘要翻译： 提供双极晶体管，其中基极电阻和基极集电极电容都减小，并且能够以高截止频率工作。 半导体器件被构造成使得发射极和非本征基极通过绝缘体侧壁和绝缘体侧壁的底面彼此分离，并且发射极大致在同一平面上。 外部基极和集电极区域通过绝缘体彼此分离。

    Bipolar transistor and manufacting method thereof
    10.
    发明授权
    Bipolar transistor and manufacting method thereof 失效
    双极晶体管及其制造方法

    公开(公告)号：US06482710B2

    公开(公告)日：2002-11-19

    申请号：US09811559

    申请日：2001-03-20

    申请人： Katsuya Oda ,  Eiji Ohue ,  Masao Kondo ,  Katsuyoshi Washio ,  Masamichi Tanabe ,  Hiromi Shimamoto

    发明人： Katsuya Oda ,  Eiji Ohue ,  Masao Kondo ,  Katsuyoshi Washio ,  Masamichi Tanabe ,  Hiromi Shimamoto

    IPC分类号： H01L21331

    CPC分类号： H01L29/66287 ,  H01L29/66242 ,  H01L29/732 ,  H01L29/7378

    摘要： A bipolar transistor according to the invention is provided with structure that an intrinsic base made of single crystal Si—Ge and a base leading-out electrode are connected via a link base made of polycrystal Si—Ge by doping at high concentration, further, a part immediately under the intrinsic base has the same conductive type as that of a collector and in a peripheral part, a single crystal Si—Ge layer having the same conductive type as that of a base is provided between the intrinsic base and a collector layer. Hereby, the reduction of the resistance of the link base between the intrinsic base and the base leading-out electrode and the reduction of capacitance between the collector and the base are simultaneously realized, and a self-aligned bipolar transistor wherein capacitance between an emitter and the base and capacitance between the collector and the base are respectively small, power consumption is small and high speed operation is enabled is acquired.

    摘要翻译： 根据本发明的双极晶体管具有以下结构：由单晶Si-Ge构成的本征基极和基极引出电极通过高浓度掺杂的由多晶Si-Ge制成的连接基底连接，此外， 在本征基底之下的部分具有与集电体相同的导电类型，并且在外围部分中，在本征基极和集电极层之间设置具有与基底相同的导电类型的单晶Si-Ge层。 因此，同时实现本征基极与基极引出电极之间的基极的电阻的降低和集电极与基极之间的电容的减小，以及自对准双极晶体管，其中发射极和 集电极和基极之间的基极和电容分别小，功耗小，获得高速运行。