公开(公告)号：US07645076B2

公开(公告)日：2010-01-12

申请号：US10554618

申请日：2003-04-29

申请人： Francesco Martini ,  Pietro Montanini ,  Guido Oliveti ,  Alberto Rampulla ,  Giacomo Rossi

发明人： Francesco Martini ,  Pietro Montanini ,  Guido Oliveti ,  Alberto Rampulla ,  Giacomo Rossi

IPC分类号： G02B6/36 ,  H01L21/00

CPC分类号： G02B6/132 ,  G02B6/136 ,  G02B6/4206

摘要： A coupling structure for coupling optical radiation, i.e., light, between an optical fibre and an optical device, e.g., a laser diode or a photodiode. The coupling structure has an optical through-via which guides the optical radiation to or from the optical fibre. Light exiting the fibre travels through a guidance channel so it remains substantially confined to a narrow optical path that mimics the fibre core. Conversely, light enters the fibre after having traveled through the guidance channel. The guidance channel has a first core region, the “channel core”, having first refractive index surrounded by a second region, the “channel cladding” having a second refractive index smaller than the first refractive index. The coupling structure, including the guidance channel, is preferably made of semiconductor-based material, more preferably of silicon-based material. The guidance channel is preferably silicon oxide. The coupling structure further has a fibre drive-in element, which facilitates insertion and alignment of the optical fibre to the guidance channel.

摘要翻译： 用于耦合光纤与光学器件（例如激光二极管或光电二极管）之间的光辐射（即光）的耦合结构。 耦合结构具有将光学辐射引导到光纤或从光纤引导的光学通孔。 离开纤维的光线穿过引导通道，因此其基本上被限制在模拟纤维芯的窄光路上。 相反，光线穿过引导通道后进入光纤。 引导通道具有第一芯区域，具有由第二区域包围的第一折射率的“沟道芯”，具有小于第一折射率的第二折射率的“沟道包层”。 包括引导通道的耦合结构优选由半导体材料制成，更优选由硅基材料制成。 引导通道优选为氧化硅。 耦合结构还具有光纤驱入元件，其有助于将光纤插入和对准引导通道。

公开(公告)号：US07629645B2

公开(公告)日：2009-12-08

申请号：US11482531

申请日：2006-07-06

申请人： Pietro Montanini ,  Marco Annese ,  Lucia Zullino

发明人： Pietro Montanini ,  Marco Annese ,  Lucia Zullino

IPC分类号： H01L29/78

CPC分类号： H01L29/66621 ,  H01L21/2652 ,  H01L29/0684 ,  H01L29/0847 ,  H01L29/6659 ,  H01L29/7834

摘要： An insulated-gate transistor includes a semiconductor layer of a first conductivity type, an insulated gate comprising a trench gate extending into the semiconductor layer, a source and a drain regions of a second conductivity type formed in the semiconductor layer at respective sides of the trench gate, wherein each one of the source and drain regions includes a first doped region, having a first dopant concentration, formed in the semiconductor layer adjacent to the trench gate, said first dopant concentration being such that a breakdown voltage of the junction formed by the first doped region and the semiconductor layer is higher than a predetermined breakdown voltage, and a second doped region, having a second dopant concentration higher than the first dopant concentration, said second doped region being formed in the first doped region and being spaced apart from the trench gate, the second dopant concentration being adapted to form a non-rectifying contact for electrically contacting the first doped region.

摘要翻译： 绝缘栅晶体管包括第一导电类型的半导体层，包括延伸到半导体层中的沟槽栅极的绝缘栅极，在沟槽的相应侧上形成在半导体层中的第二导电类型的源极和漏极区域 栅极，其中源极和漏极区域中的每一个包括形成在与沟槽栅极相邻的半导体层中的第一掺杂剂浓度的第一掺杂区域，所述第一掺杂剂浓度使得由所述栅极形成的结的击穿电压 第一掺杂区和半导体层高于预定的击穿电压，第二掺杂区具有比第一掺杂浓度高的第二掺杂浓度，所述第二掺杂区形成在第一掺杂区中并与第一掺杂区间隔开 沟槽栅极，第二掺杂剂浓度适于形成用于电连接的非整流接触 第一个掺杂区域。

公开(公告)号：US20080017949A1

公开(公告)日：2008-01-24

申请号：US11823693

申请日：2007-06-27

申请人： Pietro Montanini ,  Fabrizio Toia ,  Marta Mottura

发明人： Pietro Montanini ,  Fabrizio Toia ,  Marta Mottura

IPC分类号： H01L21/76 ,  H01L29/00

CPC分类号： H01L21/84 ,  H01L21/743 ,  H01L21/76283 ,  H01L21/76898 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

摘要： An electronic device is proposed. The device is integrated in a chip including at least one stacked layer having a front surface and a rear surface opposite the front surface, the device including: an insulating trench insulating an active region of the chip, the insulating trench having a section across each plane parallel to the front surface extending along a longitudinal line, and a front-rear contact electrically contacting the front surface to the rear surface in the active region, wherein the section of the insulating trench has a non-uniform width along the longitudinal line, and/or the device further includes at least one further insulating trench within the active region.

摘要翻译： 提出了一种电子设备。 该器件集成在包括至少一个堆叠层的芯片中，该堆叠层具有与前表面相对的前表面和后表面，该器件包括：绝缘芯片，绝缘芯片的有源区域，绝缘沟槽具有穿过每个平面的截面 平行于沿着纵向线延伸的前表面的前后接触，以及在所述有源区域中电接触所述前表面与所述后表面的前后接触，其中所述绝缘沟槽的所述部分沿着所述纵向线具有不均匀的宽度，以及 /或该器件还包括有源区内的至少一个另外的绝缘沟槽。

公开(公告)号：US20070296036A1

公开(公告)日：2007-12-27

申请号：US11820393

申请日：2007-06-19

申请人： Pietro Montanini ,  Giuseppe Ammendola ,  Riccardo Depetro ,  Marta Mottura

发明人： Pietro Montanini ,  Giuseppe Ammendola ,  Riccardo Depetro ,  Marta Mottura

IPC分类号： H01L27/12 ,  H01L21/84

CPC分类号： H01L21/84 ,  H01L21/26586 ,  H01L21/3226 ,  H01L21/76264 ,  H01L27/1207

摘要： A method for manufacturing an integrated electronic device. The method includes providing an SOI substrate having a semiconductor substrate, an insulating layer on the semiconductor substrate, and a semiconductor starting layer on the insulating layer; epitaxially growing the starting layer to obtain a semiconductor active layer on the insulating layer for integrating components of the device, and forming at least one contact trench extending from an exposed surface of the starting layer to the semiconductor substrate before the step of epitaxially growing the starting layer, wherein each contact trench clears a corresponding portion of the starting layer, of the insulating layer and of the semiconductor substrate, the epitaxial growing being further applied to the cleared portions thereby at least partially filling the at least one contact trench with semiconductor material.

摘要翻译： 一种集成电子装置的制造方法。 该方法包括提供具有半导体衬底的SOI衬底，半导体衬底上的绝缘层和绝缘层上的半导体起始层; 外延生长所述起始层以在所述绝缘层上获得用于积分所述器件的部件的半导体有源层，以及在所述起始层的外延生长步骤之前形成从所述起始层的暴露表面延伸到所述半导体衬底的至少一个接触沟槽 层，其中每个接触沟槽清除起始层，绝缘层和半导体衬底的相应部分，外延生长被进一步施加到清除部分，从而至少部分地用半导体材料填充至少一个接触沟槽。

公开(公告)号：US20070145474A1

公开(公告)日：2007-06-28

申请号：US11558285

申请日：2006-11-09

申请人： Marco Annese ,  Fabrizio Toia ,  Pietro Montanini

发明人： Marco Annese ,  Fabrizio Toia ,  Pietro Montanini

IPC分类号： H01L31/00

CPC分类号： H01L21/28167 ,  H01L29/42368 ,  H01L29/66621 ,  H01L29/7834

摘要： A vertical-gate MOS transistor is integrated in a semiconductor chip of a first conductivity type having a main surface, and includes an insulated trench gate extending into the semiconductor chip from the main surface to a gate depth. The trench gate includes a control gate and an insulation layer for insulating the control gate from the semiconductor chip, source and drain regions of a second conductivity type formed in the semiconductor chip, at least one of the source and drain regions being adjacent to the insulation layer and extending into the semiconductor chip from the main surface to a region depth lower than the gate depth. The insulation layer includes an outer portion, extending into the semiconductor chip to a protection depth less than the gate depth, and an inner portion, the outer portion having first thickness and the internal portion having a second thickness less than the first thickness.

摘要翻译： 垂直栅极MOS晶体管集成在具有主表面的第一导电类型的半导体芯片中，并且包括从主表面延伸到栅极深度的半导体芯片中的绝缘沟槽栅极。 沟槽栅极包括控制栅极和绝缘层，用于将控制栅极与形成在半导体芯片中的第二导电类型的半导体芯片，源极和漏极区域绝缘，源极和漏极区域中的至少一个与绝缘体相邻 并且从主表面延伸到半导体芯片到比栅深度低的区域。 绝缘层包括延伸到半导体芯片中的保护深度小于栅极深度的外部部分，以及内部部分，外部部分具有第一厚度，而内部部分具有小于第一厚度的第二厚度。

公开(公告)号：US20070141809A1

公开(公告)日：2007-06-21

申请号：US11584259

申请日：2006-10-19

申请人： Anna Ponza ,  Riccardo Depetro ,  Pietro Montanini

发明人： Anna Ponza ,  Riccardo Depetro ,  Pietro Montanini

IPC分类号： H01L21/00

CPC分类号： H01L21/78

摘要： A process for the fabrication of an integrated device in a semiconductor chip envisages: forming a semiconductor layer partially suspended above a semiconductor substrate and constrained to the substrate by temporary anchorages; dividing the layer into a plurality of portions laterally separated from one another; and removing the temporary anchorages, in order to free the portions.

摘要翻译： 用于制造半导体芯片中的集成器件的方法设想：形成半导体层，部分地悬置在半导体衬底之上，并通过临时锚固被约束到衬底; 将层分成彼此横向分离的多个部分; 并移除临时锚地，以释放这些部分。

公开(公告)号：US20060118164A1

公开(公告)日：2006-06-08

申请号：US11280002

申请日：2005-11-16

申请人： Pietro Montanini ,  Paolo Riboli ,  Luca Zanotti ,  Michele Palmieri ,  Marta Mottura

发明人： Pietro Montanini ,  Paolo Riboli ,  Luca Zanotti ,  Michele Palmieri ,  Marta Mottura

IPC分类号： H01L21/00 ,  H01L31/00

CPC分类号： H01L31/1804 ,  H01L31/068 ,  Y02E10/547 ,  Y02P70/521

摘要： A method of fabricating a wafer-size photovoltaic cell module includes defining an integrated cellular structure of a light converting monolateral or bilateral junction diode in an epitaxially grown detachable layer including a first deposited metal current collecting terminal of the diode. The method also includes laminating onto the surface of the processed epitaxially grown detachable layer a film of an optical grade plastic material resistant to hydrofluoric acid solutions. The method further includes immersing the wafer in a hydrofluoric acid solution causing detachment of the epitaxially grown silicon layer laminated with the film, and polishing the surface of separation of the detached epitaxially grown layer and forming a second metal current collecting terminal of the diode by masked deposition of a metal at a temperature tolerable by the film.

摘要翻译： 制造晶片尺寸光伏电池模块的方法包括在外延生长的可拆卸层中限定光转换单侧或双向结二极管的集成式蜂窝结构，其包括二极管的第一沉积金属集电端。 该方法还包括在经处理的外延生长的可剥离层的表面上层压耐氢氟酸溶液的光学级塑料材料的膜。 该方法还包括将晶片浸入氢氟酸溶液中，导致与膜层叠的外延生长的硅层脱离，并抛光分离的外延生长层的分离表面，并通过掩模形成二极管的第二金属集电端 在该膜容许的温度下沉积金属。

公开(公告)号：US20060093298A1

公开(公告)日：2006-05-04

申请号：US11258362

申请日：2005-10-25

申请人： Pietro Montanini ,  Ernestino Galeazzi ,  Paola Palmieri

发明人： Pietro Montanini ,  Ernestino Galeazzi ,  Paola Palmieri

IPC分类号： G02B6/10

CPC分类号： G02B6/1347

摘要： A waveguide core having a high coupling efficiency is disclosed. A method of manufacturing such a waveguide includes successive deposition of multiple layers of silicon dioxide. Deposition of each layer is followed by implantation of dopant impurities in a pre-established area of the layer. After deposition and implantation, high-temperature treatment is performed to diffuse the dopant impurities. The reciprocal position of the pre-established areas and the implantation dosage and energy are selected such that the refractive index of the core in the terminal segment varies gradually in a longitudinal direction, increasing towards the input/output ends of the waveguide.

摘要翻译： 公开了具有高耦合效率的波导芯。 制造这种波导的方法包括多层二氧化硅的连续沉积。 每个层的沉积之后是将掺杂剂杂质植入该层的预先建立的区域。 在沉积和植入之后，进行高温处理以扩散掺杂剂杂质。 选择预先确定的区域的相互位置和植入剂量和能量，使得端子段中的芯的折射率在纵向方向上逐渐变化，朝向波导的输入/输出端增加。