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公开(公告)号：US08183098B2
公开(公告)日：2012-05-22
申请号：US12610463
申请日：2009-11-02
IPC分类号： H01L21/762
CPC分类号： H01L21/84 , H01L21/26586 , H01L21/3226 , H01L21/76264 , H01L27/1207
摘要： A method for manufacturing an integrated electronic device. The method includes providing an SOI substrate having a semiconductor substrate, an insulating layer on the semiconductor substrate, and a semiconductor starting layer on the insulating layer; epitaxially growing the starting layer to obtain a semiconductor active layer on the insulating layer for integrating components of the device, and forming at least one contact trench extending from an exposed surface of the starting layer to the semiconductor substrate before the step of epitaxially growing the starting layer, wherein each contact trench clears a corresponding portion of the starting layer, of the insulating layer and of the semiconductor substrate, the epitaxial growing being further applied to the cleared portions thereby at least partially filling the at least one contact trench with semiconductor material.
摘要翻译： 一种集成电子装置的制造方法。 该方法包括提供具有半导体衬底的SOI衬底，半导体衬底上的绝缘层和绝缘层上的半导体起始层; 外延生长所述起始层以在所述绝缘层上获得用于积分所述器件的部件的半导体有源层，以及在所述起始层的外延生长步骤之前形成从所述起始层的暴露表面延伸到所述半导体衬底的至少一个接触沟槽 层，其中每个接触沟槽清除起始层，绝缘层和半导体衬底的相应部分，外延生长被进一步施加到清除部分，从而至少部分地用半导体材料填充至少一个接触沟槽。
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公开(公告)号：US20100075484A1
公开(公告)日：2010-03-25
申请号：US12610463
申请日：2009-11-02
IPC分类号： H01L21/762
CPC分类号： H01L21/84 , H01L21/26586 , H01L21/3226 , H01L21/76264 , H01L27/1207
摘要： A method for manufacturing an integrated electronic device. The method includes providing an SOI substrate having a semiconductor substrate, an insulating layer on the semiconductor substrate, and a semiconductor starting layer on the insulating layer; epitaxially growing the starting layer to obtain a semiconductor active layer on the insulating layer for integrating components of the device, and forming at least one contact trench extending from an exposed surface of the starting layer to the semiconductor substrate before the step of epitaxially growing the starting layer, wherein each contact trench clears a corresponding portion of the starting layer, of the insulating layer and of the semiconductor substrate, the epitaxial growing being further applied to the cleared portions thereby at least partially filling the at least one contact trench with semiconductor material.
摘要翻译： 一种集成电子装置的制造方法。 该方法包括提供具有半导体衬底的SOI衬底，半导体衬底上的绝缘层和绝缘层上的半导体起始层; 外延生长所述起始层以在所述绝缘层上获得用于积分所述器件的部件的半导体有源层，以及在所述起始层的外延生长步骤之前形成从所述起始层的暴露表面延伸到所述半导体衬底的至少一个接触沟槽 层，其中每个接触沟槽清除起始层，绝缘层和半导体衬底的相应部分，外延生长被进一步施加到清除部分，从而至少部分地用半导体材料填充至少一个接触沟槽。
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公开(公告)号：US20070296036A1
公开(公告)日：2007-12-27
申请号：US11820393
申请日：2007-06-19
CPC分类号： H01L21/84 , H01L21/26586 , H01L21/3226 , H01L21/76264 , H01L27/1207
摘要： A method for manufacturing an integrated electronic device. The method includes providing an SOI substrate having a semiconductor substrate, an insulating layer on the semiconductor substrate, and a semiconductor starting layer on the insulating layer; epitaxially growing the starting layer to obtain a semiconductor active layer on the insulating layer for integrating components of the device, and forming at least one contact trench extending from an exposed surface of the starting layer to the semiconductor substrate before the step of epitaxially growing the starting layer, wherein each contact trench clears a corresponding portion of the starting layer, of the insulating layer and of the semiconductor substrate, the epitaxial growing being further applied to the cleared portions thereby at least partially filling the at least one contact trench with semiconductor material.
摘要翻译： 一种集成电子装置的制造方法。 该方法包括提供具有半导体衬底的SOI衬底，半导体衬底上的绝缘层和绝缘层上的半导体起始层; 外延生长所述起始层以在所述绝缘层上获得用于积分所述器件的部件的半导体有源层，以及在所述起始层的外延生长步骤之前形成从所述起始层的暴露表面延伸到所述半导体衬底的至少一个接触沟槽 层，其中每个接触沟槽清除起始层，绝缘层和半导体衬底的相应部分，外延生长被进一步施加到清除部分，从而至少部分地用半导体材料填充至少一个接触沟槽。
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公开(公告)号：US07635896B2
公开(公告)日：2009-12-22
申请号：US11820393
申请日：2007-06-19
IPC分类号： H01L27/12
CPC分类号： H01L21/84 , H01L21/26586 , H01L21/3226 , H01L21/76264 , H01L27/1207
摘要： A method for manufacturing an integrated electronic device. The method includes providing an SOI substrate having a semiconductor substrate, an insulating layer on the semiconductor substrate, and a semiconductor starting layer on the insulating layer; epitaxially growing the starting layer to obtain a semiconductor active layer on the insulating layer for integrating components of the device, and forming at least one contact trench extending from an exposed surface of the starting layer to the semiconductor substrate before the step of epitaxially growing the starting layer, wherein each contact trench clears a corresponding portion of the starting layer, of the insulating layer and of the semiconductor substrate, the epitaxial growing being further applied to the cleared portions thereby at least partially filling the at least one contact trench with semiconductor material.
摘要翻译： 一种集成电子装置的制造方法。 该方法包括提供具有半导体衬底的SOI衬底，半导体衬底上的绝缘层和绝缘层上的半导体起始层; 外延生长所述起始层以在所述绝缘层上获得用于积分所述器件的部件的半导体有源层，以及在所述起始层的外延生长步骤之前形成从所述起始层的暴露表面延伸到所述半导体衬底的至少一个接触沟槽 层，其中每个接触沟槽清除起始层，绝缘层和半导体衬底的相应部分，外延生长被进一步施加到清除部分，从而至少部分地用半导体材料填充至少一个接触沟槽。
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5.发明授权公开(公告)号：US08124865B2
公开(公告)日：2012-02-28
申请号：US11280002
申请日：2005-11-16
CPC分类号： H01L31/1804 , H01L31/068 , Y02E10/547 , Y02P70/521
摘要： A method of fabricating a wafer-size photovoltaic cell module includes defining an integrated cellular structure of a light converting monolateral or bilateral junction diode in an epitaxially grown detachable layer including a first deposited metal current collecting terminal of the diode. The method also includes laminating onto the surface of the processed epitaxially grown detachable layer a film of an optical grade plastic material resistant to hydrofluoric acid solutions. The method further includes immersing the wafer in a hydrofluoric acid solution causing detachment of the epitaxially grown silicon layer laminated with the film, and polishing the surface of separation of the detached epitaxially grown layer and forming a second metal current collecting terminal of the diode by masked deposition of a metal at a temperature tolerable by the film.
摘要翻译： 制造晶片尺寸光伏电池模块的方法包括在外延生长的可拆卸层中限定光转换单侧或双向结二极管的集成式蜂窝结构，其包括二极管的第一沉积金属集电端。 该方法还包括在经处理的外延生长的可剥离层的表面上层压耐氢氟酸溶液的光学级塑料材料的膜。 该方法还包括将晶片浸入氢氟酸溶液中，导致与膜层叠的外延生长的硅层脱离，并抛光分离的外延生长层的分离表面，并通过掩模形成二极管的第二金属集电端 在该膜容许的温度下沉积金属。
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6.发明授权Front-rear contacts of electronics devices with induced defects to increase conductivity thereof 有权电子设备的前后触点具有引起的缺陷以增加其导电性公开(公告)号：US07999349B2
公开(公告)日：2011-08-16
申请号：US11823693
申请日：2007-06-27
IPC分类号： H01L23/52
CPC分类号： H01L21/84 , H01L21/743 , H01L21/76283 , H01L21/76898 , H01L27/1203 , H01L2924/0002 , H01L2924/00
摘要： An electronic device is proposed. The device is integrated in a chip including at least one stacked layer having a front surface and a rear surface opposite the front surface, the device including: an insulating trench insulating an active region of the chip, the insulating trench having a section across each plane parallel to the front surface extending along a longitudinal line, and a front-rear contact electrically contacting the front surface to the rear surface in the active region, wherein the section of the insulating trench has a non-uniform width along the longitudinal line, and/or the device further includes at least one further insulating trench within the active region.
摘要翻译： 提出了一种电子设备。 该器件集成在包括至少一个堆叠层的芯片中，该堆叠层具有与前表面相对的前表面和后表面，该器件包括：绝缘芯片，绝缘芯片的有源区域，绝缘沟槽具有穿过每个平面的截面 平行于沿着纵向线延伸的前表面的前后接触，以及在所述有源区域中电接触所述前表面与所述后表面的前后接触，其中所述绝缘沟槽的所述部分沿着所述纵向线具有不均匀的宽度，以及 /或该器件还包括有源区内的至少一个另外的绝缘沟槽。
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7.发明授权Deep contacts of integrated electronic devices based on regions implanted through trenches 有权基于通过沟槽植入的区域的集成电子设备的深度接触公开(公告)号：US08115314B2
公开(公告)日：2012-02-14
申请号：US12335285
申请日：2008-12-15
申请人： Pietro Montanini , Marta Mottura , Giuseppe Croce
发明人： Pietro Montanini , Marta Mottura , Giuseppe Croce
CPC分类号： H01L29/10 , H01L21/26586 , H01L21/743 , H01L29/1087 , H01L29/423 , H01L2924/0002 , H01L2924/00
摘要： An embodiment of an integrated circuit includes first and second semiconductor layers and a contact region disposed in the second layer. The first semiconductor layer is of a first conductivity, and the second semiconductor layer is disposed over the first layer and has a surface. The contact region is contiguous with the surface, contacts the first layer, includes a first inner conductive portion, and includes an outer conductive portion of the first conductivity. The contact region may extend deeper than conventional contact regions, because where the inner conductive portion is formed from a trench, doping the outer conductive portion via the trench may allow one to implant the dopants more deeply than conventional techniques allow.
摘要翻译： 集成电路的实施例包括第一和第二半导体层以及设置在第二层中的接触区域。 第一半导体层具有第一导电性，第二半导体层设置在第一层上并具有表面。 接触区域与表面邻接，接触第一层，包括第一内部导电部分，并且包括第一导电性的外部导电部分。 接触区域可以比常规接触区域更深，因为在内部导电部分由沟槽形成的情况下，通过沟槽掺杂外部导电部分可以使其比常规技术允许的更深入地注入掺杂剂。
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公开(公告)号：US08486741B2
公开(公告)日：2013-07-16
申请号：US13481680
申请日：2012-05-25
IPC分类号： H01L21/00 , H01L21/311 , H01L21/302
CPC分类号： H01L21/31144 , H01L21/0332 , H01L21/0334 , H01L21/31116
摘要： The described process allows trenches to be etched in a structure comprising a support substrate and a multilayer, formed on the substrate, for the definition of wave guides of an integrated optical device and comprises a selective plasma attack in the multilayer through a masking structure that leaves uncovered areas of the multilayer corresponding to the trenches to be etched. Such a masking structure is obtained by forming a mask of metallic material on the multilayer that leaves uncovered the areas corresponding to the trenches to be etched and forming a mask of non-metallic material, for example photoresist, on it that leaves uncovered regions comprising at least part of the areas and an edge portion of the mask of metallic material.
摘要翻译： 所描述的工艺允许在包括形成在衬底上的支撑衬底和多层的结构中蚀刻沟槽，用于定义集成光学器件的波导，并且包括通过掩蔽结构在多层中的选择性等离子体侵蚀 对应于要蚀刻的沟槽的多层的未覆盖区域。 这样的掩模结构是通过在多层上形成金属材料掩模而获得的，该多层不会覆盖与待蚀刻的沟槽相对应的区域，并且形成非金属材料（例如光致抗蚀剂）的掩模，其上留下未覆盖的区域， 至少部分区域和金属材料掩模的边缘部分。
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9.发明授权Deep contacts of integrated electronic devices based on regions implanted through trenches 有权基于通过沟槽植入的区域的集成电子设备的深度接触公开(公告)号：US08476143B2
公开(公告)日：2013-07-02
申请号：US13349416
申请日：2012-01-12
申请人： Pietro Montanini , Marta Mottura , Giuseppe Croce
发明人： Pietro Montanini , Marta Mottura , Giuseppe Croce
IPC分类号： H01L21/76
CPC分类号： H01L29/10 , H01L21/26586 , H01L21/743 , H01L29/1087 , H01L29/423 , H01L2924/0002 , H01L2924/00
摘要： An embodiment of an integrated circuit includes first and second semiconductor layers and a contact region disposed in the second layer. The first semiconductor layer is of a first conductivity, and the second semiconductor layer is disposed over the first layer and has a surface. The contact region is contiguous with the surface, contacts the first layer, includes a first inner conductive portion, and includes an outer conductive portion of the first conductivity. The contact region may extend deeper than conventional contact regions, because where the inner conductive portion is formed from a trench, doping the outer conductive portion via the trench may allow one to implant the dopants more deeply than conventional techniques allow.
摘要翻译： 集成电路的实施例包括第一和第二半导体层以及设置在第二层中的接触区域。 第一半导体层具有第一导电性，第二半导体层设置在第一层上并具有表面。 接触区域与表面邻接，接触第一层，包括第一内部导电部分，并且包括第一导电性的外部导电部分。 接触区域可以比常规接触区域更深，因为在内部导电部分由沟槽形成的情况下，通过沟槽掺杂外部导电部分可以使其比常规技术允许的更深入地注入掺杂剂。
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10.发明授权Method for manufacturing a vertical-gate MOS transistor with countersunk trench-gate 有权制造具有埋头沟槽栅极的垂直栅极MOS晶体管的方法公开(公告)号：US07572703B2
公开(公告)日：2009-08-11
申请号：US11558283
申请日：2006-11-09
申请人： Marco Annese , Pietro Montanini , Riccardo Depetro
发明人： Marco Annese , Pietro Montanini , Riccardo Depetro
IPC分类号： H01L21/336
CPC分类号： H01L29/1037 , H01L29/4236 , H01L29/42376 , H01L29/66621 , H01L29/78
摘要： A method manufactures a vertical-gate MOS transistor integrated in a semiconductor chip having a main surface. The method includes: forming a trench gate extending into the chip from the main surface to a gate depth, by forming a control gate and an insulation layer for insulating the control gate from the chip. Forming the trench gate includes: forming a trench extending into the chip from the main surface to a protection depth less than the gate depth, the trench having a lateral wall and a bottom wall with an edge portion of the lateral wall extending from the main surface being inclined outwardly with respect to the remaining portion of the lateral wall; forming a first auxiliary insulation layer in the trench; removing a bottom wall of the first auxiliary insulation layer; extending the trench to the gate depth; and forming a second auxiliary insulation layer in the trench.
摘要翻译： 一种制造集成在具有主表面的半导体芯片中的垂直栅极MOS晶体管的方法。 该方法包括：通过形成用于使控制栅极与芯片绝缘的控制栅极和绝缘层，形成从主表面延伸到栅极深度的沟槽栅极。 形成沟槽栅包括：形成从主表面延伸到芯片的沟槽到小于栅极深度的保护深度，沟槽具有侧壁和底壁，侧壁的边缘部分从主表面延伸 相对于侧壁的剩余部分向外倾斜; 在沟槽中形成第一辅助绝缘层; 移除所述第一辅助绝缘层的底壁; 将沟槽延伸到浇口深度; 以及在沟槽中形成第二辅助绝缘层。
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