公开(公告)号：US07551803B2

公开(公告)日：2009-06-23

申请号：US10959953

申请日：2004-10-06

Applicant: Pascal Urard ,  Laurent Paumier ,  Yan Meroth

Inventor： Pascal Urard ,  Laurent Paumier ,  Yan Meroth

IPC: G06K9/32

CPC classification number: G06T1/60 ,  G09G5/391

Abstract: An image adapter transforms an input image into an output image by successively processing tiles and by changing numbers of columns and of rows of image points. The image adapter includes queue memories connected in series so as to receive values associated with the points of a tile of the input image. A module for calculating a weighted average possesses inputs connected respectively to an output of one of the memories. The module produces values sampled in a direction parallel to the columns and corresponding to the values associated with points of the input image. A sampling rate converter, connected to the output of the module, produces values associated with the points of the output image according to a sampling rate determined for a direction parallel to the rows.

Abstract translation: 图像适配器通过连续地处理图块并且通过改变图像点的列和行的数量将输入图像转换成输出图像。 图像适配器包括串联连接的队列存储器，以便接收与输入图像的图块的点相关联的值。 用于计算加权平均的模块具有分别连接到其中一个存储器的输出的输入。 该模块产生在平行于列的方向上采样的值，并对应于与输入图像的点相关联的值。 连接到模块的输出的采样率转换器根据与行平行的方向确定的采样率产生与输出图像的点相关联的值。

公开(公告)号：US20090031094A1

公开(公告)日：2009-01-29

申请号：US12150599

申请日：2008-04-29

Applicant: Cyrille Chavet ,  Pascal Urard ,  Philippe Coussy ,  Eric Martin

Inventor： Cyrille Chavet ,  Pascal Urard ,  Philippe Coussy ,  Eric Martin

IPC: G06F12/06 ,  G06F12/00

CPC classification number: H03M13/2775 ,  H03M13/2957 ,  H04L1/0071

Abstract: A data interleaving device is provided that includes an input, an output, and a data interleaver coupled to the input and the output. The input receives data originating from a plurality of processing blocks. The output transfers interleaved data to the plurality of processing blocks. The data interleaver includes a controller, at least one interconnection module, and a plurality of memories. The controller prepares a data-to-memory assignment data structure. The at least one interconnection module switches data in parallel according to the data-to-memory assignment data structure and acts identically on all data switched simultaneously in parallel. The plurality of memories store the switched data. The data interleaver interleaves data received from the input and provides the interleaved data at the output.

Abstract translation: 提供了一种包括耦合到输入和输出的输入，输出和数据交织器的数据交织装置。 输入接收来自多个处理块的数据。 输出将交错数据传送到多个处理块。 数据交织器包括控制器，至少一个互连模块和多个存储器。 控制器准备数据到内存分配数据结构。 至少一个互连模块根据数据到存储器分配数据结构并行地切换数据，并且对并行地同时切换的所有数据执行相同的操作。 多个存储器存储切换的数据。 数据交织器交织从输入接收的数据，并在输出端提供交错数据。

公开(公告)号：US07454693B2

公开(公告)日：2008-11-18

申请号：US11158718

申请日：2005-06-22

Applicant: Pascal Urard ,  Laurent Paumier

Inventor： Pascal Urard ,  Laurent Paumier

IPC: G06F11/00

CPC classification number: H03M13/6566 ,  H03M13/1137

Abstract: An LDPC decoder having a determined number of processing units operating in parallel, storage circuitry capable of containing first words containing a juxtaposition of messages of a first type, and second words containing a juxtaposition of messages of a second type, a message provision unit capable of providing each processing unit with a message of the first type or a message of the second type, and a message write unit capable of writing, into the storage circuitry, first words or second words. The message provision unit is capable of providing a message at a position in a word which depends on the word or the message write unit is capable of writing each message at a position in the word which depends on the word.

Abstract translation: 具有确定数量的处理单元并行操作的LDPC解码器，能够包含包含第一类型的消息的并置的第一个字的存储电路和包含第二类型的消息并置的第二个字，能够 向每个处理单元提供第一类型的消息或第二类型的消息;以及消息写入单元，其能够向存储电路写入第一字或第二字。 消息提供单元能够在单词中的位置处提供消息，该单词取决于单词或消息写入单元能够将每个消息写入取决于单词的单词中的位置。

公开(公告)号：US07308618B2

公开(公告)日：2007-12-11

申请号：US10880334

申请日：2004-06-29

Applicant: Pascal Urard ,  Laurent Paumier ,  Etiene Lantreibecq

Inventor： Pascal Urard ,  Laurent Paumier ,  Etiene Lantreibecq

IPC: G11C29/00

CPC classification number: H03M13/6502 ,  H03M13/27 ,  H03M13/2785 ,  H03M13/6566

Abstract: An interleaver includes two random access memories for storing data and an addressing device (100) linked to respective address inputs of the two memories. The addressing device is designed to transmit, at each instant of a clock, a cue for read access to one of the two memories and a cue for write access to the other of the two memories, so that, at each instant, a data item is written to or read from each memory.

Abstract translation: 交织器包括用于存储数据的两个随机存取存储器和连接到两个存储器的相应地址输入的寻址装置（100）。 寻址装置被设计成在时钟的每个时刻发送用于对两个存储器之一的读取访问的提示和用于对两个存储器中的另一个的写入访问的提示，使得在每个时刻，数据项 被写入或读取每个存储器。

公开(公告)号：US20070094565A1

公开(公告)日：2007-04-26

申请号：US11534476

申请日：2006-09-22

Applicant: Laurent Paumier ,  Pascal Urard ,  Martial Comminges

Inventor： Laurent Paumier ,  Pascal Urard ,  Martial Comminges

IPC: H03M13/00

CPC classification number: H03M13/6505 ,  H03M13/1105 ,  H03M13/1134 ,  H03M13/1137 ,  H03M13/1165 ,  H03M13/6566

Abstract: A system implemented for example in the form of an SoC comprises a first demodulator for generating a first data stream to be decoded, and a second demodulator for generating a second data stream to be decoded, and a block decoder. The block decoder comprises an input memory for storing blocks of data from the first data stream and blocks of data from the second data stream, and a block decoding unit for processing, from the input memory, the blocks of data from the first and second data streams.

Abstract translation: 以例如SoC形式实现的系统包括用于产生要解码的第一数据流的第一解调器和用于产生待解码的第二数据流的第二解调器和块解码器。 块解码器包括用于存储来自第一数据流的数据块和来自第二数据流的数据块的输入存储器，以及块解码单元，用于从输入存储器处理来自第一和第二数据的数据块 流。

公开(公告)号：US07032165B2

公开(公告)日：2006-04-18

申请号：US10357561

申请日：2003-02-04

Applicant: Pascal Urard ,  Thierry Valentin

Inventor： Pascal Urard ,  Thierry Valentin

IPC: H03M13/03

CPC classification number: H03M13/3961 ,  H03M13/4107

Abstract: A device for implementing a function of add-compare-select type in an error correction code decoder, having first and second adders for adding, respectively for first and second branches, branch metric values, intermediate value of former state metrics, and values of former state metric offset, thus forming first and second values of present state metrics; a comparator, coupled to the first and second adders, for selecting the highest value from among the first and second values; circuitry for determining a digital value of present state metric offset including a single bit, based on the first and second values.

公开(公告)号：US20050283703A1

公开(公告)日：2005-12-22

申请号：US11158516

申请日：2005-06-22

Applicant: Pascal Urard ,  Laurent Paumier

Inventor： Pascal Urard ,  Laurent Paumier

IPC: H03M13/00 ,  H03M13/11 ,  H04N7/16

CPC classification number: H03M13/1137 ,  H03M13/1105

Abstract: An LDPC decoder comprising a determined number of processing units operating in parallel, a storage means capable of containing first words containing a juxtaposition of messages of a first type, and second words containing a juxtaposition of messages of a second type, a message provision unit capable of providing each processing unit with a message of the first type or a message of the second type, and a message write unit capable of writing, into the storage means, first words or second words. The message provision unit is capable of providing a message at a position in a word which depends on the word or the message write unit is capable of writing each message at a position in the word which depends on the word.

Abstract translation: 包括确定数量的并行操作的处理单元的LDPC解码器，能够包含包含第一类型的消息的并置的第一个字的存储装置和包含第二类型的消息的并置的第二字，能够 向每个处理单元提供第一类型的消息或第二类型的消息，以及能够将存储装置中的第一个字或第二个字写入的消息写入单元。 消息提供单元能够在单词中的位置处提供消息，该单词取决于单词或消息写入单元能够将每个消息写入取决于单词的单词中的位置。

公开(公告)号：US20050111752A1

公开(公告)日：2005-05-26

申请号：US10959953

申请日：2004-10-06

Applicant: Pascal Urard ,  Laurent Paumier ,  Yan Meroth

Inventor： Pascal Urard ,  Laurent Paumier ,  Yan Meroth

IPC: G06K9/36 ,  G09G5/391 ,  H04N3/22 ,  H04N9/77

CPC classification number: G06T1/60 ,  G09G5/391

Abstract: An image adapter transforms an input image into an output image by successively processing tiles and by changing numbers of columns and of rows of image points. The image adapter includes queue memories connected in series so as to receive values associated with the points of a tile of the input image. A module for calculating a weighted average possesses inputs connected respectively to an output of one of the memories. The module produces values sampled in a direction parallel to the columns and corresponding to the values associated with points of the input image. A sampling rate converter, connected to the output of the module, produces values associated with the points of the output image according to a sampling rate determined for a direction parallel to the rows.

Abstract translation: 图像适配器通过连续地处理图块并且通过改变图像点的列和行的数量将输入图像转换成输出图像。 图像适配器包括串联连接的队列存储器，以便接收与输入图像的图块的点相关联的值。 用于计算加权平均的模块具有分别连接到其中一个存储器的输出的输入。 该模块产生在平行于列的方向上采样的值，并对应于与输入图像的点相关联的值。 连接到模块的输出的采样率转换器根据与行平行的方向确定的采样率产生与输出图像的点相关联的值。