公开(公告)号：US08384231B2

公开(公告)日：2013-02-26

申请号：US12689126

申请日：2010-01-18

申请人： Gordon M. Grivna ,  Michael J. Seddon

发明人： Gordon M. Grivna ,  Michael J. Seddon

IPC分类号： H01L23/28

CPC分类号： H01L25/0655 ,  H01L21/78 ,  H01L23/3171 ,  H01L23/49575 ,  H01L25/16 ,  H01L29/0657 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： In one embodiment, semiconductor die having non-rectangular shapes and die having various different shapes are formed and singulated from a semiconductor wafer.

公开(公告)号：US08247296B2

公开(公告)日：2012-08-21

申请号：US12633967

申请日：2009-12-09

申请人： Gordon M. Grivna

发明人： Gordon M. Grivna

IPC分类号： H01L21/336

CPC分类号： H01L29/7811 ,  H01L29/0878 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42372 ,  H01L29/4933 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7813

摘要： A method for forming a transistor having insulated gate electrodes and insulated shield electrodes within trench regions includes forming dielectric stack overlying a substrate. The dielectric stack includes a first layer of one material overlying the substrate and a second layer of a different material overlying the first layer. Trench regions are formed adjacent to the dielectric stack. After the insulated shield electrodes are formed, the method includes removing the second layer and then forming the insulated gate electrodes. Portions of gate electrode material are removed to form first recessed regions, and dielectric plugs are formed in the first recessed regions using the first layer as a stop layer. The first layer is then removed, and spacers are formed adjacent the dielectric plugs. Second recessed regions are formed in the substrate self-aligned to the spacers.

摘要翻译： 在沟槽区域内形成具有绝缘栅电极和绝缘屏蔽电极的晶体管的方法包括形成覆盖在衬底上的电介质叠层。 电介质堆叠包括覆盖衬底的一种材料的第一层和覆盖第一层的不同材料的第二层。 沟槽区域形成在与电介质叠层相邻的位置。 在形成绝缘屏蔽电极之后，该方法包括去除第二层，然后形成绝缘栅电极。 去除部分栅电极材料以形成第一凹陷区域，并且使用第一层作为停止层在第一凹陷区域中形成介电塞。 然后去除第一层，并且在电介质塞附近形成间隔物。 在与衬垫自对准的衬底中形成第二凹陷区域。

公开(公告)号：US08222115B2

公开(公告)日：2012-07-17

申请号：US13398356

申请日：2012-02-16

申请人： David D. Marreiro ,  Sudhama C. Shastri ,  Gordon M. Grivna ,  Earl D. Fuchs

发明人： David D. Marreiro ,  Sudhama C. Shastri ,  Gordon M. Grivna ,  Earl D. Fuchs

IPC分类号： H01L21/20

CPC分类号： H01L27/0814 ,  H01L29/8618 ,  H01L29/93 ,  Y10S438/963 ,  Y10S438/983

摘要： In one embodiment, high doped semiconductor channels are formed in a semiconductor region of an opposite conductivity type to increase the capacitance of the device.

摘要翻译： 在一个实施例中，高掺杂半导体沟道形成在相反导电类型的半导体区域中以增加器件的电容。

公开(公告)号：US08207037B2

公开(公告)日：2012-06-26

申请号：US11931606

申请日：2007-10-31

申请人： Hui Wang ,  Gennadiy Nemtsev ,  Yingping Zheng ,  Gordon M. Grivna

发明人： Hui Wang ,  Gennadiy Nemtsev ,  Yingping Zheng ,  Gordon M. Grivna

IPC分类号： H01L21/8236

CPC分类号： H01L29/407 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/456 ,  H01L29/4925 ,  H01L29/4933 ,  H01L29/513 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811

摘要： A semiconductor component that includes a field plate and a semiconductor device and a method of manufacturing the semiconductor component. A semiconductor material includes an epitaxial layer disposed on a semiconductor substrate. A trench having an upper portion and a lower portion is formed in the epitaxial layer. A portion of a field plate is formed in the lower portion of the trench, wherein the field plate is electrically isolated from trench sidewalls. A gate structure is formed in the upper portion of the trench, wherein a gate oxide is formed from opposing sidewalls of the trench. Gate electrodes are formed adjacent to the gate oxide formed from the opposing sidewalls and a dielectric material is formed adjacent to the gate electrode. Another portion of the field plate is formed in the upper portion of the trench and cooperates with the portion of the field plate formed in the lower portion of the trench to form the field plate.

摘要翻译： 包括场板和半导体器件的半导体部件以及半导体部件的制造方法。 半导体材料包括设置在半导体衬底上的外延层。 在外延层中形成具有上部和下部的沟槽。 场板的一部分形成在沟槽的下部，其中场板与沟槽侧壁电隔离。 栅极结构形成在沟槽的上部，其中栅极氧化物由沟槽的相对的侧壁形成。 栅电极与由相对的侧壁形成的栅极氧化物相邻形成，并且与栅电极相邻形成电介质材料。 场板的另一部分形成在沟槽的上部，并且与形成在沟槽的下部中的场板的部分配合以形成场板。

公开(公告)号：US08049309B2

公开(公告)日：2011-11-01

申请号：US12499429

申请日：2009-07-08

申请人： Gordon M. Grivna ,  Shanghui L. Tu

发明人： Gordon M. Grivna ,  Shanghui L. Tu

IPC分类号： H01L23/488

CPC分类号： H01L29/7811 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

摘要： In one embodiment, an edge seal region of a semiconductor die is formed by forming a first dielectric layer on a surface of a semiconductor substrate near an edge of the semiconductor die and extending across into a scribe grid region of the semiconductor substrate. Another dielectric layer is formed overlying the first dielectric layer. An opening is formed through the first and second dielectric layers. The second dielectric layer is used as a mask for forming a doped region on the semiconductor substrate through the opening. A metal is formed that electrically contacts the doped region and an exterior edge of the first dielectric layer within the opening.

摘要翻译： 在一个实施例中，半导体管芯的边缘密封区域通过在半导体管芯的边缘附近的半导体衬底的表面上形成第一介电层而形成，并延伸到半导体衬底的划线栅格区域中。 形成覆盖在第一电介质层上的另一电介质层。 通过第一和第二介电层形成开口。 第二电介质层用作通过开口在半导体衬底上形成掺杂区的掩模。 形成与开口内的第一电介质层的掺杂区域和外部边缘电接触的金属。

公开(公告)号：US20110193160A1

公开(公告)日：2011-08-11

申请号：US12702055

申请日：2010-02-08

申请人： Gary H. Loechelt ,  Gordon M. Grivna ,  Peter J. Zdebel

发明人： Gary H. Loechelt ,  Gordon M. Grivna ,  Peter J. Zdebel

IPC分类号： H01L27/088 ,  H01L21/8234

CPC分类号： H01L29/66696 ,  H01L21/26586 ,  H01L21/2815 ,  H01L21/743 ,  H01L21/823475 ,  H01L27/1203 ,  H01L29/0626 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/0847 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/1008 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/4175 ,  H01L29/42376 ,  H01L29/6625 ,  H01L29/66659 ,  H01L29/66689 ,  H01L29/735 ,  H01L29/7824 ,  H01L29/7835 ,  H01L2924/0002 ,  H01L2924/00

摘要： An electronic device can include a buried conductive region, a buried insulating layer over the buried conductive region, and a semiconductor layer disposed over the buried insulating layer, wherein the semiconductor layer has a primary surface and an opposing surface, and the buried conductive region is disposed closer to the opposing surface than to the primary surface. The electronic device can also include a current-carrying electrode of a first transistor, wherein the current carrying electrode is disposed along the primary surface and spaced apart from the buried conductive layer. The electronic device can also include a vertical conductive structure extending through the buried insulating layer, wherein the vertical conductive structure is electrically connected to the current-carrying electrode and the buried conductive region.

摘要翻译： 电子器件可以包括掩埋导电区域，掩埋导电区域上的掩埋绝缘层和设置在掩埋绝缘层上的半导体层，其中半导体层具有主表面和相对表面，并且掩埋导电区域 相对于主表面更靠近对置的表面。 电子设备还可以包括第一晶体管的载流电极，其中载流电极沿着主表面设置并与掩埋的导电层间隔开。 电子器件还可以包括延伸穿过掩埋绝缘层的垂直导电结构，其中垂直导电结构电连接到载流电极和掩埋导电区域。

公开(公告)号：US20100072573A1

公开(公告)日：2010-03-25

申请号：US12630670

申请日：2009-12-03

申请人： David D. Marreiro ,  Sudhama C. Shastri ,  Gordon M. Grivna ,  Earl D. Fuchs

发明人： David D. Marreiro ,  Sudhama C. Shastri ,  Gordon M. Grivna ,  Earl D. Fuchs

IPC分类号： H01L29/861 ,  H01L21/02

CPC分类号： H01L27/0814 ,  H01L29/8618 ,  H01L29/93 ,  Y10S438/963 ,  Y10S438/983

摘要： In one embodiment, high doped semiconductor channels are formed in a semiconductor region of an opposite conductivity type to increase the capacitance of the device.

摘要翻译： 在一个实施例中，高掺杂半导体沟道形成在相反导电类型的半导体区域中以增加器件的电容。

公开(公告)号：US07679146B2

公开(公告)日：2010-03-16

申请号：US11442706

申请日：2006-05-30

申请人： Shanghui Larry Tu ,  Gordon M. Grivna

发明人： Shanghui Larry Tu ,  Gordon M. Grivna

IPC分类号： H01L27/088

CPC分类号： H01L29/7813 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/0886 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734

摘要： In one embodiment, a semiconductor device is formed having sub-surface charge compensation regions in proximity to channel regions of the device. The charge compensation trenches comprise at least two opposite conductivity type semiconductor layers. A channel connecting region electrically couples the channel region to one of the at least two opposite conductivity type semiconductor layers.

摘要翻译： 在一个实施例中，形成半导体器件，其具有靠近器件沟道区的子表面电荷补偿区域。 电荷补偿沟槽包括至少两个相反导电类型的半导体层。 沟道连接区域将沟道区域电耦合到所述至少两个相反导电型半导体层中的一个。

公开(公告)号：US20090267204A1

公开(公告)日：2009-10-29

申请号：US12499429

申请日：2009-07-08

申请人： Gordon M. Grivna ,  Shanghui L. Tu

发明人： Gordon M. Grivna ,  Shanghui L. Tu

IPC分类号： H01L23/488 ,  H01L23/498

CPC分类号： H01L29/7811 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

摘要： In one embodiment, an edge seal region of a semiconductor die is formed by forming a first dielectric layer on a surface of a semiconductor substrate near an edge of the semiconductor die and extending across into a scribe grid region of the semiconductor substrate. Another dielectric layer is formed overlying the first dielectric layer. An opening is formed through the first and second dielectric layers. The second dielectric layer is used as a mask for forming a doped region on the semiconductor substrate through the opening. A metal is formed that electrically contacts the doped region and an exterior edge of the first dielectric layer within the opening.

摘要翻译： 在一个实施例中，半导体管芯的边缘密封区域通过在半导体管芯的边缘附近的半导体衬底的表面上形成第一介电层而形成，并延伸到半导体衬底的划线栅格区域中。 形成覆盖在第一电介质层上的另一电介质层。 通过第一和第二介电层形成开口。 第二电介质层用作通过开口在半导体衬底上形成掺杂区的掩模。 形成与开口内的第一电介质层的掺杂区域和外部边缘电接触的金属。

公开(公告)号：US20090108343A1

公开(公告)日：2009-04-30

申请号：US11931994

申请日：2007-10-31

申请人： Gennadiy Nemtsev ,  Hui Wang ,  Yingping Zheng ,  Gordon M. Grivna

发明人： Gennadiy Nemtsev ,  Hui Wang ,  Yingping Zheng ,  Gordon M. Grivna

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811

摘要： A semiconductor component that includes a field plate and a semiconductor device and a method of manufacturing the semiconductor component. A semiconductor material includes an epitaxial layer disposed on a semiconductor substrate. Field plate trenches extend into the semiconductor material and field plates are formed in the field plate trenches. A gate trench is formed between two adjacent field plate trenches and another gate trench is formed adjacent one of the field plate trenches. Gate structures are formed in the gate trenches, wherein each gate structure includes a gate oxide and a gate conductor. A conductor electrically couples the field plates together.

摘要翻译： 包括场板和半导体器件的半导体部件以及半导体部件的制造方法。 半导体材料包括设置在半导体衬底上的外延层。 场板沟槽延伸到半导体材料中，并且场板形成在场板槽中。 在两个相邻的场板沟槽之间形成栅极沟槽，并且在一个栅极板沟槽附近形成另一个栅极沟槽。 栅极结构形成在栅极沟槽中，其中每个栅极结构包括栅极氧化物和栅极导体。 导体将场板电耦合在一起。