公开(公告)号：US11899099B2

公开(公告)日：2024-02-13

申请号：US16698601

申请日：2019-11-27

Applicant: QUALCOMM Incorporated

Inventor： Radhika Dilip Gowaikar ,  Ravi Teja Sukhavasi ,  Daniel Hendricus Franciscus Fontijne ,  Bence Major ,  Amin Ansari ,  Teck Yian Lim ,  Sundar Subramanian ,  Xinzhou Wu

IPC: G01S13/931 ,  G01S7/41 ,  G01S13/86 ,  G05D1/00 ,  G05D1/02 ,  G06T7/60 ,  G06V20/56 ,  G06F18/25 ,  G06F18/22 ,  G06F18/213 ,  G06V10/80

CPC classification number: G01S13/931 ,  G01S7/417 ,  G01S13/867 ,  G05D1/0088 ,  G05D1/0231 ,  G05D1/0257 ,  G06F18/213 ,  G06F18/22 ,  G06F18/253 ,  G06T7/60 ,  G06V10/80 ,  G06V20/56 ,  G01S2013/9318 ,  G01S2013/9319 ,  G01S2013/9321 ,  G01S2013/93185 ,  G01S2013/93276 ,  G05D2201/0213 ,  G06T2207/10044 ,  G06T2207/30252

Abstract: Disclosed are techniques for fusing camera and radar frames to perform object detection in one or more spatial domains. In an aspect, an on-board computer of a host vehicle receives, from a camera sensor of the host vehicle, a plurality of camera frames, receives, from a radar sensor of the host vehicle, a plurality of radar frames, performs a camera feature extraction process on a first camera frame of the plurality of camera frames to generate a first camera feature map, performs a radar feature extraction process on a first radar frame of the plurality of radar frames to generate a first radar feature map, converts the first camera feature map and/or the first radar feature map to a common spatial domain, and concatenates the first radar feature map and the first camera feature map to generate a first concatenated feature map in the common spatial domain.

公开(公告)号：US10296076B2

公开(公告)日：2019-05-21

申请号：US15156156

申请日：2016-05-16

Applicant: QUALCOMM Incorporated

Inventor： Javid Jaffari ,  Amin Ansari

IPC: G06F1/3296 ,  G06F1/08 ,  G06F1/28 ,  G06F1/30 ,  G06F1/3206 ,  G06F1/324

Abstract: Supply voltage droop management circuits for reducing or avoiding supply voltage droops are disclosed. A supply voltage droop management circuit includes interrupt circuit configured to receive event signals generated by a functional circuit. Event signals correspond to an operational event that occurs in the functional circuit and increases load current demand to a power supply powering the functional circuit, causing supply voltage droop. The interrupt circuit is configured to generate an interrupt signal in response to the received event signal. Memory includes an operational event-frequency table having entries with a target frequency corresponding to an operational event. Operating the functional circuit at target frequency reduces the load current demand on the power supply, and supply voltage droop. A clock control circuit is configured to receive interrupt signal, access memory to determine the target frequency, and generate clock frequency adjustment signal to cause clock generator to adjust to the target frequency.

公开(公告)号：US10176147B2

公开(公告)日：2019-01-08

申请号：US15452299

申请日：2017-03-07

Applicant: QUALCOMM Incorporated

Inventor： Kambiz Samadi ,  Amin Ansari ,  Yang Du

IPC: G06F9/30 ,  G06F15/80 ,  H01L21/00 ,  H01L25/00 ,  H01L27/00 ,  G06F9/38 ,  G06F12/0875 ,  G06F15/76 ,  H01L21/822 ,  H01L25/065 ,  H01L27/06

Abstract: Multi-processor core three-dimensional (3D) integrated circuits (ICs) (3DICs) and related methods are disclosed. In aspects disclosed herein, ICs are provided that include a central processing unit (CPU) having multiple processor cores (“cores”) to improve performance. To further improve CPU performance, the multiple cores can also be designed to communicate with each other to offload workloads and/or share resources for parallel processing, but at a communication overhead associated with passing data through interconnects which have an associated latency. To mitigate this communication overhead inefficiency, aspects disclosed herein provide the CPU with its multiple cores in a 3DIC. Because 3DICs can overlap different IC tiers and/or align similar components in the same IC tier, the cores can be designed and located between or within different IC tiers in a 3DIC to reduce communication distance associated with processor core communication to share workload and/or resources, thus improving performance of the multi-processor CPU design.

公开(公告)号：US09998143B2

公开(公告)日：2018-06-12

申请号：US15230325

申请日：2016-08-05

Applicant: QUALCOMM Incorporated

Inventor： Richard Senior ,  Amin Ansari ,  Jinxia Bai ,  Vito Bica

IPC: H03M7/30

CPC classification number: H03M7/3088 ,  H03M7/30 ,  H03M7/3086 ,  H03M7/6005

Abstract: A system for data decompression may include a processor coupled to a remote memory having a remote dictionary stored thereon and coupled to a decompression logic having a local memory with a local dictionary. The processor may decompress data during execution by accessing the local dictionary, and if necessary, the remote dictionary.

公开(公告)号：US20170329391A1

公开(公告)日：2017-11-16

申请号：US15156156

申请日：2016-05-16

Applicant: QUALCOMM Incorporated

Inventor： Javid Jaffari ,  Amin Ansari

IPC: G06F1/32 ,  G06F1/28 ,  G06F1/08

CPC classification number: G06F1/3296 ,  G06F1/08 ,  G06F1/28 ,  G06F1/305 ,  G06F1/3206 ,  G06F1/324 ,  Y02D10/126

Abstract: Supply voltage droop management circuits for reducing or avoiding supply voltage droops are disclosed. A supply voltage droop management circuit includes interrupt circuit configured to receive event signals generated by a functional circuit. Event signals correspond to an operational event that occurs in the functional circuit and increases load current demand to a power supply powering the functional circuit, causing supply voltage droop. The interrupt circuit is configured to generate an interrupt signal in response to the received event signal. Memory includes an operational event-frequency table having entries with a target frequency corresponding to an operational event. Operating the functional circuit at target frequency reduces the load current demand on the power supply, and supply voltage droop. A clock control circuit is configured to receive interrupt signal, access memory to determine the target frequency, and generate clock frequency adjustment signal to cause clock generator to adjust to the target frequency.

公开(公告)号：US20170269851A1

公开(公告)日：2017-09-21

申请号：US15074444

申请日：2016-03-18

Applicant: QUALCOMM Incorporated

Inventor： Andres Alejandro Oportus Valenzuela ,  Amin Ansari ,  Richard Senior ,  Nieyan Geng ,  Anand Janakiraman ,  Gurvinder Singh Chhabra

IPC: G06F3/06 ,  G06F12/08

CPC classification number: G06F3/0611 ,  G06F3/0626 ,  G06F3/0659 ,  G06F3/0661 ,  G06F3/0665 ,  G06F3/0673 ,  G06F12/023 ,  G06F12/0284 ,  G06F12/0615 ,  G06F12/0897 ,  G06F2212/1016 ,  G06F2212/1024 ,  G06F2212/1041 ,  G06F2212/1044 ,  G06F2212/1056 ,  G06F2212/152 ,  G06F2212/401 ,  G06F2212/65

Abstract: Aspects disclosed relate to a priority-based access of compressed memory lines in a processor-based system. In an aspect, a memory access device in the processor-based system receives a read access request for memory. If the read access request is higher priority, the memory access device uses the logical memory address of the read access request as the physical memory address to access the compressed memory line. However, if the read access request is lower priority, the memory access device translates the logical memory address of the read access request into one or more physical memory addresses in memory space left by the compression of higher priority lines. In this manner, the efficiency of higher priority compressed memory accesses is improved by removing a level of indirection otherwise required to find and access compressed memory lines.