公开(公告)号：US11552015B2

公开(公告)日：2023-01-10

申请号：US16900672

申请日：2020-06-12

Applicant: QUALCOMM Incorporated

Inventor： Aniket Patil ,  Hong Bok We ,  Kuiwon Kang

IPC: H01L23/528 ,  H01L23/00 ,  H01L27/146 ,  H01L39/24 ,  H01L21/768

Abstract: A substrate that includes a core layer comprising a first surface and a second surface, a plurality of core interconnects located in the core layer, a high-density interconnect portion located in the core layer, a first dielectric layer coupled to the first surface of the core layer, a first plurality of interconnects located in the first dielectric layer, a second dielectric layer coupled to the second surface of the core layer, and a second plurality of interconnects located in the second dielectric layer. The high-density interconnect portion includes a first redistribution dielectric layer and a first plurality of high-density interconnects located in the first redistribution dielectric layer. The high-density interconnect portion may provide high-density interconnects.

公开(公告)号：US11342254B2

公开(公告)日：2022-05-24

申请号：US16819732

申请日：2020-03-16

Applicant: QUALCOMM Incorporated

Inventor： Joan Rey Villarba Buot ,  Kuiwon Kang ,  Joonsuk Park ,  Karthikeyan Dhandapani

IPC: H05K1/03 ,  H05K1/11 ,  H01L23/498 ,  H01L21/48

Abstract: Certain aspects of the present disclosure generally relate to an embedded trace substrate having at least two different dielectric layers with different dielectric materials and methods for fabricating the same. One example embedded trace substrate generally includes a first metal layer; a first dielectric layer disposed below the first metal layer and comprising a first dielectric material; a second dielectric layer disposed below the first dielectric layer and comprising a second dielectric material, wherein the second dielectric material of the second dielectric layer is stiffer than the first dielectric material of the first dielectric layer; and a second metal layer disposed below the second dielectric layer.

公开(公告)号：US20210242160A1

公开(公告)日：2021-08-05

申请号：US16921152

申请日：2020-07-06

Applicant: QUALCOMM Incorporated

Inventor： Kuiwon Kang ,  Aniket Patil ,  Bohan Yan ,  Dongming He

IPC: H01L23/00 ,  H01L23/367 ,  H01L23/532

Abstract: Integrated circuit (IC) packages employing a thermal conductive semiconductor package substrate with die region split and related fabrication methods are disclosed. The package substrate includes a die split where metal contacts in one or more dielectric layers of the package substrate underneath the IC die(s) are thicker (e.g., in a core die region) than other metal contacts (e.g., in a peripheral die region) in the dielectric layer. This facilitates higher thermal dissipation from the IC die(s) through the thicker metal contacts in the package substrate. Cross-talk shielding of the package substrate may not be sacrificed since thinner metal contacts of the package substrate that carry high speed signaling can be of lesser thickness than the thicker metal contacts that provide higher thermal dissipation. The dielectric layer in the package substrate may also include dielectric materials having different thermal conductivities to further facilitate thermal dissipation and/or desired electrical or mechanical characteristics.

公开(公告)号：US10804195B2

公开(公告)日：2020-10-13

申请号：US16230896

申请日：2018-12-21

Applicant: QUALCOMM Incorporated

Inventor： Kuiwon Kang ,  Marcus Hsu ,  Brigham Navaja ,  Houssam Jomaa

IPC: H01L23/522 ,  H01L23/00 ,  H01L21/768 ,  H01L23/528

Abstract: A device that includes a die and a substrate coupled to the die. The substrate includes a dielectric layer and a plurality of embedded interconnects. Each embedded interconnect located through a first planar surface of the substrate such that a first portion of the embedded interconnect is located within the dielectric layer and a second portion of the embedded interconnect is external of the dielectric layer. In some implementations, the substrate includes a core layer. In some implementations, the dielectric layer and the plurality of embedded interconnects may be part of a build up layer of the substrate.

公开(公告)号：US09370097B2

公开(公告)日：2016-06-14

申请号：US13783168

申请日：2013-03-01

Applicant: QUALCOMM Incorporated

Inventor： Chin-Kwan Kim ,  Kuiwon Kang ,  Omar James Bchir

IPC: H05K7/10 ,  H05K1/11 ,  G01R31/28 ,  H05K1/02 ,  H05K3/34

CPC classification number: H05K1/111 ,  G01R31/2818 ,  H05K1/0268 ,  H05K3/3452 ,  H05K2201/10674 ,  Y10T29/49004 ,  Y10T29/49124 ,  Y10T29/4913

Abstract: Some implementations provide a substrate that includes several traces, a solder resist layer covering the several traces, and a testing pad coupled to a trace from the several traces. The testing pad is at least partially exposed and at least partially free of the solder resist layer when a chip is coupled to the substrate. In some implementations, the several traces have a pitch that is 100 microns (μm) or less. In some implementations, the substrate is a package substrate. In some implementations, the package substrate is a package substrate on which a thermal compression flip chip is mounted during an assembly process. In some implementations, the testing pad is free of a direct connection with a bonding component of the chip when the chip is coupled to the substrate. In some implementations, the bonding component is one of a solder ball.

Abstract translation: 一些实施方案提供了包括几条迹线的衬底，覆盖几条迹线的阻焊层，以及耦合到几条迹线的迹线的测试焊盘。 当芯片耦合到衬底时，测试焊盘至少部分地暴露并且至少部分地不含阻焊层。 在一些实施方案中，多个迹线具有100微米（μm）或更小的间距。 在一些实施方式中，衬底是封装衬底。 在一些实施方案中，封装衬底是在组装过程期间安装热压缩倒装芯片的封装衬底。 在一些实施方案中，当芯片耦合到衬底时，测试焊盘不与芯片的焊接部件直接连接。 在一些实施方式中，接合部件是焊球之一。