公开(公告)号：US09483600B2

公开(公告)日：2016-11-01

申请号：US14645336

申请日：2015-03-11

Applicant: QUALCOMM Incorporated

Inventor： Mamta Bansal ,  Uday Doddannagari ,  Paras Gupta ,  Ramaprasath Vilangudipitchai ,  Parissa Najdesamii ,  Dorav Kumar ,  Nitin Partani

IPC: H01L25/00 ,  G06F17/50 ,  H01L27/02 ,  H04W72/04 ,  H01L23/528 ,  H01L27/092

CPC classification number: G06F17/5077 ,  G06F17/5072 ,  H01L23/5286 ,  H01L27/0207 ,  H01L27/092 ,  H01L2924/0002 ,  H04W72/0453 ,  Y02D70/00 ,  H01L2924/00

Abstract: A MOS device includes a number of standard cells configured to reduce routing congestions while providing area savings on the MOS device. The standard cells may be single height standard cells that share an n-type well isolated from other nearby n-type wells. The input and output signal pins of the single height standard cells may be configured in a lowest possible metal layer (e.g., M1), while the secondary power pins of the single height standard cells may be configured in a higher metal layer (e.g., M2). Interconnects supplying power to secondary power pins may be configured along vertical tracks and shared among different sets of standard cells, which may reduce the number of vertical tracks used in the MOS device. The number of available horizontal routing tracks in the MOS device may remain unaffected, since the horizontal tracks already used by the primary power/ground mesh are used for power connection.

Abstract translation: MOS器件包括多个标准单元，其被配置为减少路由拥塞，同时在MOS器件上提供区域节省。 标准细胞可以是共享与其他附近n型孔分离的n型井的单高度标准细胞。 单个高度标准单元的输入和输出信号引脚可以配置在最低可能的金属层（例如，M1）中，而单高度标准单元的次级电源引脚可以配置在较高的金属层（例如，M2 ）。 为次级电源引脚供电的互连可以沿着垂直轨道配置，并在不同的标准单元组之间共享，这可以减少在MOS器件中使用的垂直轨道的数量。 MOS器件中可用的水平路由轨迹的数量可能不受影响，因为主电源/接地网格已经使用的水平轨迹用于电源连接。

公开(公告)号：US09473113B1

公开(公告)日：2016-10-18

申请号：US14864101

申请日：2015-09-24

Applicant: QUALCOMM Incorporated

Inventor： Harshat Pant ,  Ramaprasath Vilangudipitchai ,  Divjyot Bhan ,  Lipeng Cao ,  Sai Pradeep Kochuri ,  Parissa Najdesamii

IPC: H03K3/02 ,  H03K3/012 ,  H03K3/037

CPC classification number: H03K3/012 ,  H03K3/0372 ,  H03K3/0375 ,  H03K3/356008 ,  H03K3/35625

Abstract: An integrated circuit (IC) is disclosed herein for managing power with flip-flops having a retention feature. In an example aspect, an IC includes a constant power rail, a collapsible power rail, multiple flip-flops, and power management circuitry. Each flip-flop of the multiple flip-flops includes a master portion that is coupled to the collapsible power rail and a slave portion that is coupled to the constant power rail. The power management circuitry is configured to combine a clock signal and a retention signal into a combined control signal and to provide the combined control signal to each flip-flop of the multiple flip-flops.

Abstract translation: 本文公开了一种用于通过具有保持特征的触发器来管理电力的集成电路（IC）。 在示例方面，IC包括恒定电源轨，可折叠电源轨，多个触发器和电源管理电路。 多个触发器的每个触发器包括耦合到可折叠电源轨的主部和耦合到恒功率轨的从部。 功率管理电路被配置为将时钟信号和保持信号组合成组合的控制信号，并将组合的控制信号提供给多个触发器的每个触发器。

公开(公告)号：US08971098B1

公开(公告)日：2015-03-03

申请号：US14023382

申请日：2013-09-10

Applicant: QUALCOMM Incorporated

Inventor： Gaurav Bhargava ,  Ramaprasath Vilangudipitchai ,  Ohsang Kwon

IPC: G11C11/00 ,  G11C29/00 ,  G11C7/00

CPC classification number: G11C29/10 ,  G11C29/022 ,  G11C29/32

Abstract: A latch-based array includes a plurality of columns and rows. Each column comprises a plurality of slave latches that all latch in parallel a master-latched data output from the column's master latch during normal operation. In a fault-testing mode of operation, one of the slaves in the column latches an inverted version of the master-latched data output while the remaining slave latches in the column latch the master-latched data output. In this fashion, the slave latches are decorrelated in a single write operation.

Abstract translation: 基于闩锁的阵列包括多个列和行。 每列包括多个从锁存器，它们在正常操作期间并行地从锁存器的主锁存器输出的主锁存数据并行锁存。 在故障测试操作模式下，列中的一个从站锁存主锁存数据输出的反向版本，而列中剩余的从锁存器锁存主锁存数据输出。 以这种方式，从锁存器在单次写入操作中被去相关。

公开(公告)号：US08848429B2

公开(公告)日：2014-09-30

申请号：US13767788

申请日：2013-02-14

Applicant: QUALCOMM Incorporated

Inventor： Ramaprasath Vilangudipitchai ,  Gaurav Bhargava ,  Ohsang Kwon

IPC: G11C11/00 ,  G11C7/22

CPC classification number: G11C7/22 ,  G11C2207/007

Abstract: A latch-based memory includes a plurality of slave latches arranged in rows and columns. Each column of slave latches receives a latched data signal from a corresponding master latch. Each row includes a clock gating circuit and a corresponding reset circuit. If a row is active for a write operation, the active row's clock gating circuit passes a write clock to the active row's slave latches. Conversely, the clock gating circuit for an inactive row gates the write clock to the inactive row's slave latches by passing a held version of the write clock in a first clock state to the inactive row's slave latches. While a reset signal is asserted, each reset circuit gates the write clock by passing the held version of the write clock in the first clock state to the slave latches in the reset circuit's row.

Abstract translation: 基于锁存器的存储器包括以行和列排列的多个从锁存器。 每列从锁存器从相应的主锁存器接收锁存的数据信号。 每行包括时钟门控电路和相应的复位电路。 如果一行对于写操作有效，则活动行的时钟选通电路将写时钟传递到活动行的从锁存器。 相反，用于非活动行的时钟门控电路通过将第一时钟状态的写入时钟的保持版本传递到非活动行的从锁存器来将写时钟门禁到非活动行的从锁存器。 当复位信号被断言时，每个复位电路通过将第一时钟状态下的写入时钟的保持版本传送到复位电路行中的从锁存器来对写时钟进行门控。