公开(公告)号：US09473113B1

公开(公告)日：2016-10-18

申请号：US14864101

申请日：2015-09-24

Applicant: QUALCOMM Incorporated

Inventor： Harshat Pant ,  Ramaprasath Vilangudipitchai ,  Divjyot Bhan ,  Lipeng Cao ,  Sai Pradeep Kochuri ,  Parissa Najdesamii

IPC: H03K3/02 ,  H03K3/012 ,  H03K3/037

CPC classification number: H03K3/012 ,  H03K3/0372 ,  H03K3/0375 ,  H03K3/356008 ,  H03K3/35625

Abstract: An integrated circuit (IC) is disclosed herein for managing power with flip-flops having a retention feature. In an example aspect, an IC includes a constant power rail, a collapsible power rail, multiple flip-flops, and power management circuitry. Each flip-flop of the multiple flip-flops includes a master portion that is coupled to the collapsible power rail and a slave portion that is coupled to the constant power rail. The power management circuitry is configured to combine a clock signal and a retention signal into a combined control signal and to provide the combined control signal to each flip-flop of the multiple flip-flops.

Abstract translation: 本文公开了一种用于通过具有保持特征的触发器来管理电力的集成电路（IC）。 在示例方面，IC包括恒定电源轨，可折叠电源轨，多个触发器和电源管理电路。 多个触发器的每个触发器包括耦合到可折叠电源轨的主部和耦合到恒功率轨的从部。 功率管理电路被配置为将时钟信号和保持信号组合成组合的控制信号，并将组合的控制信号提供给多个触发器的每个触发器。

公开(公告)号：US09654101B2

公开(公告)日：2017-05-16

申请号：US14814409

申请日：2015-07-30

Applicant: QUALCOMM Incorporated

Inventor： Lipeng Cao ,  Divjyot Bhan ,  Ramaprasath Vilangudipitchai ,  Dorav Kumar

IPC: H03K17/693 ,  H03K19/00

CPC classification number: H03K17/693 ,  H03K19/0016

Abstract: An integrated circuit (IC) is disclosed herein for power management through power rail multiplexing. In an example aspect, an IC includes a first power rail, a second power rail, and a load power rail. The IC also includes a first set of transistors including first transistors that are coupled to the first power rail and a second set of transistors including second transistors that are coupled to the second power rail. The IC further includes power-multiplexer circuitry that is configured to switch access to power for the load power rail from the first power rail to the second power rail by sequentially turning off the first transistors of the first set of transistors and then sequentially turning on the second transistors of the second set of transistors.

公开(公告)号：US09665160B1

公开(公告)日：2017-05-30

申请号：US15156859

申请日：2016-05-17

Applicant: QUALCOMM Incorporated

Inventor： Lipeng Cao ,  Divjyot Bhan ,  Harshat Pant ,  Ramaprasath Vilangudipitchai

IPC: H03K3/356 ,  G06F1/32 ,  H03K3/3562 ,  H03K5/08 ,  G06F13/364

CPC classification number: G06F1/324 ,  G06F1/3287 ,  G06F13/364 ,  H03K3/0372 ,  H03K3/0375 ,  H03K3/3562 ,  H03K5/08 ,  Y02D10/171

Abstract: An integrated circuit (IC) is disclosed having a unified control scheme and a unifying architecture for different types of retention flip-flops (RFFs). In an example aspect, an IC includes a constant power rail to provide power during a power collapse period and a collapsible power rail to cease providing power during the power collapse period. The IC also includes a positive-edge-triggered (PET) RFF and a negative-edge-triggered (NET) RFF. The PET RFF includes a master portion and a slave portion, with the slave portion coupled to the constant power rail and the master portion coupled to the collapsible power rail. The NET RFF includes master and slave portions, with the master portion coupled to the constant power rail and the slave portion coupled to the collapsible power rail. In another example aspect, a control signal based on a clock and a retention signal may be routed to both RFFs.

公开(公告)号：US10109619B2

公开(公告)日：2018-10-23

申请号：US15174684

申请日：2016-06-06

Applicant: QUALCOMM Incorporated

Inventor： Harshat Pant ,  Mohammed Yousuff Shariff ,  Parissa Najdesamii ,  Ramaprasath Vilangudipitchai ,  Divjyot Bhan

IPC: H01L23/538 ,  H01L27/02 ,  H01L23/535 ,  H01L27/088 ,  G06F17/50 ,  H01L21/8238

Abstract: In an aspect of the disclosure, a MOS device for reducing routing congestion caused by using split n-well cells in a merged n-well circuit block is provided. The MOS device may include a first set of cells adjacent to each other in a first direction. The MOS device may include a second set of cells adjacent to each other in the first direction and adjacent to the first set of cells in a second direction. The second set of cells each may include a first n-well, a second n-well, and a third n-well separated from each other. The MOS device may include an interconnect extending in the first direction in the second set of cells. The interconnect may provide a voltage source to the first n-well of each of the second set of cells.

公开(公告)号：US20170033796A1

公开(公告)日：2017-02-02

申请号：US14814409

申请日：2015-07-30

Applicant: QUALCOMM Incorporated

Inventor： Lipeng Cao ,  Divjyot Bhan ,  Ramaprasath Vilangudipitchai ,  Dorav Kumar

IPC: H03K17/693

CPC classification number: H03K17/693 ,  H03K19/0016

Abstract: An integrated circuit (IC) is disclosed herein for power management through power rail multiplexing. In an example aspect, an IC includes a first power rail, a second power rail, and a load power rail. The IC also includes a first set of transistors including first transistors that are coupled to the first power rail and a second set of transistors including second transistors that are coupled to the second power rail. The IC further includes power-multiplexer circuitry that is configured to switch access to power for the load power rail from the first power rail to the second power rail by sequentially turning off the first transistors of the first set of transistors and then sequentially turning on the second transistors of the second set of transistors.

Abstract translation: 本文公开了一种用于通过电力轨道复用进行电力管理的集成电路（IC）。 在示例方面，IC包括第一电力轨，第二电力轨和负载电力轨。 IC还包括第一组晶体管，其包括耦合到第一电力轨的第一晶体管和包括耦合到第二电力轨的第二晶体管的第二组晶体管。 IC还包括电力多路复用器电路，其被配置为通过顺序地关闭第一组晶体管的第一晶体管，然后顺序地接通第一组晶体管的第一晶体管，从而将负载电源轨从第一电力轨到第二电力轨的电​​力切换 第二组晶体管的第二晶体管。