公开(公告)号：US20170083422A1

公开(公告)日：2017-03-23

申请号：US15080450

申请日：2016-03-24

Applicant: QUALCOMM Incorporated

Inventor： Scott Wang-Yip Cheng ,  Raheel Khan ,  Kanwal Banga

IPC: G06F11/26 ,  G06F11/27 ,  G06F11/263

CPC classification number: G06F11/261 ,  G06F11/263 ,  G06F11/27 ,  H04L1/241

Abstract: Various aspects describe an on-chip, hardware error-generator component. In some cases, the hardware error-generator component connects to a data path between two components contained within a same chip. Upon receiving an error simulation input, the hardware error-generator component modifies data being transmitted on the data path by inserting a data pattern that simulates an error condition. Alternately or additionally, the hardware error-generator randomly alters one or more of the transmitted data bits.

公开(公告)号：US20150222323A1

公开(公告)日：2015-08-06

申请号：US14170274

申请日：2014-01-31

Applicant: QUALCOMM INCORPORATED

Inventor： Raheel Khan ,  Gayatri Singaravelu

IPC: H04B1/7115 ,  H04B1/7083 ,  H04B1/7117

CPC classification number: H04B1/7115 ,  H04B1/707 ,  H04B1/708 ,  H04B1/7083 ,  H04B1/7117

Abstract: Systems and methods for despreading a received signal are described herein. In one embodiment, a vector processor comprises a plurality of code generators, wherein each code generator is configured to generate a different code corresponding to a different code hypothesis. The vector processor also comprises a plurality of despread blocks coupled to a common input for receiving samples of a signal, wherein each despread block is configured to despread at least a portion of the samples with a different one of the codes to generate respective despreaded samples and to accumulate the respective despreaded samples over a length of the code.

Abstract translation: 在此描述用于解扩接收信号的系统和方法。 在一个实施例中，向量处理器包括多个代码生成器，其中每个代码生成器被配置为生成对应于不同代码假设的不同代码。 矢量处理器还包括耦合到公共输入的多个解扩展块，用于接收信号的采样，其中每个去扩展块被配置为用不同的一个代码对至少一部分样本进行解扩，以产生相应的解扩样本， 以在代码的长度上累积各个解扩的样本。

公开(公告)号：US20140281370A1

公开(公告)日：2014-09-18

申请号：US13798641

申请日：2013-03-13

Applicant: QUALCOMM INCORPORATED

Inventor： Raheel Khan

IPC: G06F9/30

CPC classification number: G06F9/30036 ,  G06F9/3887 ,  G06F9/3897 ,  G06F15/7867 ,  G06F15/8053 ,  Y02D10/12 ,  Y02D10/13

Abstract: Embodiments disclosed herein include vector processing engines (VPEs) having programmable data path configurations for providing multi-mode vector processing. Related vector processors, systems, and methods are also disclosed. The VPEs include a vector processing stage(s) configured to process vector data according to a vector instruction executed in the vector processing stage. Each vector processing stage includes vector processing blocks each configured to process vector data based on the vector instruction being executed. The vector processing blocks are capable of providing different vector operations for different types of vector instructions based on data path configurations. Data paths of the vector processing blocks are programmable to be reprogrammable to process vector data differently according to the particular vector instruction being executed. In this manner, a VPE can be provided with its data paths configuration programmable to execute different types of functions based on data path configuration according to the vector instruction being executed.

Abstract translation: 本文公开的实施例包括具有用于提供多模式向量处理的可编程数据路径配置的向量处理引擎（VPE）。 还公开了相关的矢量处理器，系统和方法。 VPE包括被配置为根据在矢量处理阶段中执行的矢量指令来处理矢量数据的矢量处理级。 每个矢量处理级包括矢量处理块，每个矢量处理块被配置为基于正在执行的矢量指令来处理矢量数据。 向量处理块能够基于数据路径配置为不同类型的向量指令提供不同的向量操作。 矢量处理块的数据路径可编程为可重新编程，以根据正在执行的特定向量指令不同地处理矢量数据。 以这种方式，可以为VPE提供可编程的数据路径配置，以根据正在执行的向量指令，基于数据路径配置来执行不同类型的功能。

公开(公告)号：US20140280420A1

公开(公告)日：2014-09-18

申请号：US13798599

申请日：2013-03-13

Applicant: QUALCOMM INCORPORATED

Inventor： Raheel Khan

IPC: G06F17/14

CPC classification number: G06F17/142 ,  G06F7/5443 ,  G06F9/3001 ,  G06F9/30036 ,  G06F9/3887 ,  G06F9/3897 ,  G06F15/8053 ,  G06F2207/382

Abstract: Vector processing engines (VPEs) having programmable data path configurations for providing multi-mode Radix-2X butterfly vector processing circuits. Related vector processors, systems, and methods are also disclosed. The VPEs disclosed herein include a plurality of vector processing stages each having vector processing blocks that have programmable data path configurations for performing Radix-2X butterfly vector operations to perform Fast Fourier Transform (FFT) vector processing operations efficiently. The data path configurations of the vector processing blocks can be programmed to provide different types of Radix-2X butterfly vector operations as well as other arithmetic logic vector operations. As a result, fewer VPEs can provide desired Radix-2X butterfly vector operations and other types arithmetic logic vector operations in a vector processor, thus saving area in the vector processor while still retaining vector processing advantages of fewer register writes and faster vector instruction execution times over scalar processing engines.

Abstract translation: 具有可编程数据路径配置的矢量处理引擎（VPE），用于提供多模Radix-2X蝴蝶向量处理电路。 还公开了相关的矢量处理器，系统和方法。 本文公开的VPE包括多个矢量处理级，每个矢量处理级具有矢量处理块，该矢量处理块具有用于执行基数-2X蝶矢量运算的可编程数据路径配置，以有效地执行快速傅里叶变换（FFT）矢量处理操作。 矢量处理块的数据路径配置可以被编程为提供不同类型的Radix-2X蝴蝶向量运算以及其他算术逻辑矢量运算。 因此，较少的VPE可以在向量处理器中提供期望的Radix-2X蝴蝶向量操作和其他类型的算术逻辑向量操作，从而节省向量处理器中的区域，同时仍然保留较少寄存器写入和更快矢量指令执行时间的向量处理优点 超标量处理引擎。

公开(公告)号：US20140280407A1

公开(公告)日：2014-09-18

申请号：US13798618

申请日：2013-03-13

Applicant: QUALCOMM INCORPORATED

Inventor： Raheel Khan

IPC: G06F7/575

CPC classification number: G06F7/575 ,  G06F7/5443 ,  G06F9/30036 ,  G06F9/3887 ,  G06F9/3897 ,  G06F15/8053 ,  G06F2207/382 ,  G06F2207/3828

Abstract: Embodiments disclosed herein include vector processing carry-save accumulators employing redundant carry-save format to reduce carry propagation. The multi-mode vector processing carry-save accumulators employing redundant carry-save format can be provided in a vector processing engine (VPE) to perform vector accumulation operations. Related vector processors, systems, and methods are also disclosed. The accumulator blocks are configured as carry-save accumulator structures. The accumulator blocks are configured to accumulate in redundant carry-save format so that carrys and saves are accumulated and saved without the need to provide a carry propagation path and a carry propagation add operation during each step of accumulation. A carry propagate adder is only required to propagate the accumulated carry once at the end of the accumulation. In this manner, power consumption and gate delay associated with performing a carry propagation add operation during each step of accumulation in the accumulator blocks is reduced or eliminated.

Abstract translation: 本文公开的实施例包括采用冗余进位 - 保存格式以减少进位传播的向量处理进位存储器。 可以在矢量处理引擎（VPE）中提供采用冗余进位 - 保存格式的多模式向量处理进位存储器，以执行向量累加操作。 还公开了相关的矢量处理器，系统和方法。 蓄电池块被配置为进位保存蓄电池结构。 累加器块被配置为以冗余进位 - 保存格式累积，从而累加和保存进位和保存，而不需要在每个累积步骤期间提供进位传播路径和进位传播加法运算。 进位传播加法器只需要在累加结束时传播累积的进位一次。 以这种方式，降低或消除了在累加器块中的累积的每个步骤期间执行进位传播添加操作相关联的功耗和门延迟。