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40 条记录 (耗时 0.024 秒)

    Device fabrication by anisotropic wet etch
    31.
    发明申请
    Device fabrication by anisotropic wet etch 失效
    通过各向异性湿法蚀刻的器件制造

    公开(公告)号：US20070166900A1

    公开(公告)日：2007-07-19

    申请号：US11333108

    申请日：2006-01-17

    申请人： Yujun Li ,  Kenneth Settlemyer ,  Jochen Beintner

    发明人： Yujun Li ,  Kenneth Settlemyer ,  Jochen Beintner

    IPC分类号： H01L21/8232 ,  H01L21/335 ,  H01L21/84 ,  H01L21/00

    CPC分类号： H01L21/84 ,  H01L21/30608 ,  H01L27/1203 ,  H01L29/045 ,  H01L29/66772 ,  H01L29/66818 ,  H01L29/785

    摘要： A method of fabrication and a field effect device structure are presented that reduce source/drain capacitance and allow for device body contact. A Si based material pedestal is produced, the top surface and the sidewalls of which are oriented in a way to be substantially parallel with selected crystallographic planes of the pedestal and of a supporting member. The pedestal is wet etched with an anisotropic solution containing ammonium hydroxide. The sidewalls of the pedestal become faceted forming a segment in the pedestal with a reduced cross section. The dopant concentration in the reduced cross section segment is chosen to be sufficiently high for it to provide for electrical continuity through the pedestal.

    摘要翻译： 提出了一种制造方法和场效应器件结构，其减少源/漏电容并允许器件接触。 制造基于Si的材料基座，其顶表面和其侧壁的取向方向基本上平行于基座和支撑构件的选定结晶平面。 用包含氢氧化铵的各向异性溶液湿式蚀刻基座。 基座的侧壁变小，在基座上形成截面减小的部分。 选择减小的横截面段中的掺杂剂浓度足够高以使其提供穿过基座的电连续性。

    Vertical MOSFET with dual work function materials
    32.
    发明申请
    Vertical MOSFET with dual work function materials 失效
    具有双功能材料的垂直MOSFET

    公开(公告)号：US20060163631A1

    公开(公告)日：2006-07-27

    申请号：US10622477

    申请日：2003-07-18

    申请人： Xiangdong Chen ,  Geng Wang ,  Yujun Li ,  Qiqing Ouyang

    发明人： Xiangdong Chen ,  Geng Wang ,  Yujun Li ,  Qiqing Ouyang

    IPC分类号： H01L29/94

    CPC分类号： H01L29/66181 ,  H01L27/10864

    摘要： A vertical pass transistor used in a DRAM cell for maintaining a low total leakage current and providing adequate drive current is described together with a method of fabricating such a device. The transistor gate is engineered in lieu of the channel. The vertical pass transistor for the DRAM cell incorporates two gate materials having different work functions. The gate material near the storage node is n-type doped polysilicon. The gate material near the bit line diffusion is made of silicide or metal having a higher work function than the n-polysilicon. The novel device structure shows several advantages: the channel doping is reduced while maintaining a high Vt and a low sub-threshold leakage current; the carrier mobility improves with the reduced channel doping; the body effect of the device is reduced which improves the write back current; and the sub-threshold swing is reduced because of the low channel doping.

    摘要翻译： 在DRAM单元中使用的用于保持低总漏电流并提供足够的驱动电流的垂直传输晶体管与制造这种器件的方法一起被描述。 晶体管栅极被设计代替通道。 用于DRAM单元的垂直传输晶体管包括具有不同功函数的两个栅极材料。 存储节点附近的栅极材料为n型掺杂多晶硅。 位线扩散附近的栅极材料由具有比n-多晶硅更高的功函数的硅化物或金属制成。 该新颖的器件结构显示出几个优点：沟道掺杂减少，同时保持高Vt和低的亚阈值漏电流; 载流子迁移率随着沟道掺杂的降低而提高; 减少了器件的体效，提高了回写电流; 并且由于低通道掺杂，子阈值摆幅减小。

    Structure and method of forming a notched gate field effect transistor
    33.
    发明申请
    Structure and method of forming a notched gate field effect transistor 审中-公开
    形成陷波栅场效应晶体管的结构和方法

    公开(公告)号：US20060157805A1

    公开(公告)日：2006-07-20

    申请号：US11266245

    申请日：2005-11-04

    申请人： Jochen Beintner ,  Yujun Li ,  Naim Moumen ,  Porshia Wrschka

    发明人： Jochen Beintner ,  Yujun Li ,  Naim Moumen ,  Porshia Wrschka

    IPC分类号： H01L29/94

    CPC分类号： H01L29/6659 ,  H01L21/26586 ,  H01L21/28044 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/49 ,  H01L29/665 ,  Y10S438/933

    摘要： A structure and method of forming a notched gate MOSFET. A gate dielectric is formed on the surface of an active area on the semiconductor substrate. A layer of polysilicon is then deposited on the gate dielectric. This step is followed by depositing a layer of silicon germanium. The sidewalls of the polysilicon layer are then laterally etched, selective to the SiGe layer to create a notched gate conductor structure, with the SiGe layer being broader than the underlying polysilicon layer. Sidewall spacers are preferably formed on sidewalls of the SiGe layer and the polysilicon layer. A silicide layer is preferably formed as a self-aligned silicide from a polysilicon layer deposited over the SiGe layer. One or more other processing steps are preferably performed in completing the transistor.

    摘要翻译： 形成缺口栅极MOSFET的结构和方法。 栅电介质形成在半导体衬底上的有源区的表面上。 然后在栅极电介质上沉积多晶硅层。 该步骤之后是沉积一层硅锗。 然后横向蚀刻多晶硅层的侧壁，对SiGe层有选择性，以产生刻蚀的栅极导体结构，其中SiGe层比下面的多晶硅层宽。 侧壁间隔物优选形成在SiGe层和多晶硅层的侧壁上。 硅化物层优选从沉积在SiGe层上的多晶硅层形成为自对准硅化物。 优选在完成晶体管时执行一个或多个其它处理步骤。

    Device fabrication by anisotropic wet etch
    35.
    发明授权
    Device fabrication by anisotropic wet etch 失效
    通过各向异性湿法蚀刻的器件制造

    公开(公告)号：US07410844B2

    公开(公告)日：2008-08-12

    申请号：US11333108

    申请日：2006-01-17

    申请人： Yujun Li ,  Kenneth T. Settlemyer, Jr. ,  Jochen Beintner

    发明人： Yujun Li ,  Kenneth T. Settlemyer, Jr. ,  Jochen Beintner

    IPC分类号： H01L21/336

    CPC分类号： H01L21/84 ,  H01L21/30608 ,  H01L27/1203 ,  H01L29/045 ,  H01L29/66772 ,  H01L29/66818 ,  H01L29/785

    摘要： A method of fabrication and a field effect device structure are presented that reduce source/drain capacitance and allow for device body contact. A Si based material pedestal is produced, the top surface and the sidewalls of which are oriented in a way to be substantially parallel with selected crystallographic planes of the pedestal and of a supporting member. The pedestal is wet etched with an anisotropic solution containing ammonium hydroxide. The sidewalls of the pedestal become faceted forming a segment in the pedestal with a reduced cross section. The dopant concentration in the reduced cross section segment is chosen to be sufficiently high for it to provide for electrical continuity through the pedestal.

    摘要翻译： 提出了一种制造方法和场效应器件结构，其减少源/漏电容并允许器件接触。 产生基于Si的材料基座，其顶表面和其侧壁的方向定位成与基座和支撑构件的选定结晶平面基本平行。 用包含氢氧化铵的各向异性溶液湿式蚀刻基座。 基座的侧壁变小，在基座上形成截面减小的部分。 选择减小的横截面段中的掺杂剂浓度足够高以使其提供穿过基座的电连续性。

    Corner clipping for field effect devices
    36.
    发明申请
    Corner clipping for field effect devices 有权
    场效应装置的角剪

    公开(公告)号：US20070167024A1

    公开(公告)日：2007-07-19

    申请号：US11333109

    申请日：2006-01-17

    申请人： Yujun Li ,  Kenneth Settlemyer ,  Jochen Beintner

    发明人： Yujun Li ,  Kenneth Settlemyer ,  Jochen Beintner

    IPC分类号： H01L21/302 ,  H01L21/461

    CPC分类号： H01L21/30608 ,  H01L29/045 ,  H01L29/66795 ,  H01L29/7853

    摘要： A method is presented for fabricating a non-planar field effect device. The method includes the production of a Si based material Fin structure that has a top surface substantially in parallel with a {111} crystallographic plane of the Si Fin structure, and the etching of the Si Fin structure with a solution which contains ammonium hydroxide (NH4OH). In this manner, due to differing etch rates in ammonium hydroxide of various Si based material crystallographic planes, the corners on the Fin structure become clipped, and angles between the horizontal and vertical planes of the Fin structure increase. A FinFET device with clipped, or rounded, corners is then fabricated to completion. In a typical embodiment the FinFET device is selected to be a silicon-on-insulator (SOI) device.

    摘要翻译： 提出了一种用于制造非平面场效应器件的方法。 该方法包括生产Si基材料Fin结构，其具有与Si Fin结构的{111}晶面大致平行的顶表面，并且用含有氢氧化铵（NH）的溶液蚀刻Si Fin结构 4 OH）。 以这种方式，由于各种Si基材料结晶面的氢氧化铵中的蚀刻速率不同，Fin结构上的拐角被限制，Fin结构的水平和垂直平面之间的角度增加。 然后制造具有夹角或圆角的FinFET器件以完成。 在典型的实施例中，FinFET器件被选择为绝缘体上硅（SOI）器件。

    METHOD OF FORMING A MOSFET WITH DUAL WORK FUNCTION MATERIALS
    37.
    发明申请
    METHOD OF FORMING A MOSFET WITH DUAL WORK FUNCTION MATERIALS 有权
    形成具有双功能功能材料的MOSFET的方法

    公开(公告)号：US20070051996A1

    公开(公告)日：2007-03-08

    申请号：US11553072

    申请日：2006-10-26

    申请人： Xiangdong Chen ,  Geng Wang ,  Yujun Li ,  Qiqing Ouyang

    发明人： Xiangdong Chen ,  Geng Wang ,  Yujun Li ,  Qiqing Ouyang

    IPC分类号： H01L29/94

    CPC分类号： H01L29/66181 ,  H01L27/10864

    摘要： A vertical pass transistor used in a DRAM cell for maintaining a low total leakage current and providing adequate drive current is described together with a method of fabricating such a device. The transistor gate is engineered in lieu of the channel. The vertical pass transistor for the DRAM cell incorporates two gate materials having different work functions. The gate material near the storage node is n-type doped polysilicon. The gate material near the bit line diffusion is made of silicide or metal having a higher work function than the n-polysilicon. The novel device structure shows several advantages: the channel doping is reduced while maintaining a high Vt and a low sub-threshold leakage current; the carrier mobility improves with the reduced channel doping; the body effect of the device is reduced which improves the write back current; and the sub-threshold swing is reduced because of the low channel doping.

    摘要翻译： 在DRAM单元中使用的用于保持低总漏电流并提供足够的驱动电流的垂直传输晶体管与制造这种器件的方法一起被描述。 晶体管栅极被设计代替通道。 用于DRAM单元的垂直传输晶体管包括具有不同功函数的两个栅极材料。 存储节点附近的栅极材料为n型掺杂多晶硅。 位线扩散附近的栅极材料由具有比n-多晶硅更高的功函数的硅化物或金属制成。 该新颖的器件结构显示出几个优点：沟道掺杂减少，同时保持高Vt和低的亚阈值漏电流; 载流子迁移率随着沟道掺杂的降低而提高; 减少了器件的体效，提高了回写电流; 并且由于低通道掺杂，子阈值摆幅减小。

    Hair conditioning composition comprising tight lamellar gel matrix
    38.
    发明申请
    Hair conditioning composition comprising tight lamellar gel matrix 审中-公开
    包含紧密层状凝胶基质的头发调理组合物

    公开(公告)号：US20060078528A1

    公开(公告)日：2006-04-13

    申请号：US11249617

    申请日：2005-10-13

    申请人： Jian-Zhong Yang ,  Koji Takata ,  Yujun Li ,  Hoyun Kim

    发明人： Jian-Zhong Yang ,  Koji Takata ,  Yujun Li ,  Hoyun Kim

    IPC分类号： A61K8/41

    CPC分类号： A61K8/898 ,  A61K8/342 ,  A61K8/361 ,  A61K8/416 ,  A61K8/891 ,  A61Q5/12

    摘要： Disclosed is a hair conditioning composition comprising: a cationic surfactant; a high melting point fatty compound; and an aqueous carrier; wherein the cationic surfactant, the high melting point fatty compound, and the aqueous carrier form a lamellar gel matrix; wherein the d-spacing of the lamellar layers is in the range of 33 nm or less; and wherein the composition has a yield stress of about 30 Pa or more at 26.7° C. The composition of the present invention can provide improved conditioning benefits, especially improved slippery feel during the application to wet hair.

    摘要翻译： 公开了一种头发调理组合物，其包含：阳离子表面活性剂; 高熔点脂肪化合物; 和水性载体; 其中所述阳离子表面活性剂，所述高熔点脂肪族化合物和所述水性载体形成层状凝胶基质; 其中所述层状层的d间距在33nm以下的范围内; 并且其中所述组合物在26.7℃下具有约30Pa或更高的屈服应力。本发明的组合物可以提供改善的调理效果，特别是在应用于湿发期间改善的滑溜感。

    Self-aligned channel implantation
    40.
    发明授权
    Self-aligned channel implantation 失效
    自对准通道植入

    公开(公告)号：US06329271B1

    公开(公告)日：2001-12-11

    申请号：US09588244

    申请日：2000-06-06

    申请人： Hiroyuki Akatsu ,  Yujun Li ,  Jochen Beintner

    发明人： Hiroyuki Akatsu ,  Yujun Li ,  Jochen Beintner

    IPC分类号： H01L21425

    CPC分类号： H01L29/66583 ,  H01L21/823412 ,  H01L29/105

    摘要： A short channel insulated gate field effect transistor has within the semiconductor body that houses the transistor a buried layer of the same conductivity type as the body but of higher impurity concentration. The buried layer is below the channel region and essentially extends only the distance between the drain and source regions of the transistor. The process to form the device provides high concentration in the region under the gate to suppress lateral depletion region expansion, while keeping a gradual junction in the vertical direction.

    摘要翻译： 短沟道绝缘栅场效应晶体管在半导体本体内部具有与晶体管相同的导电类型的掩埋层，但具有较高的杂质浓度。 掩埋层在沟道区下方，并且基本上只延伸晶体管的漏极和源极区之间的距离。 形成器件的过程在栅极下方的区域提供高浓度，以抑制横向耗尽区域膨胀，同时保持垂直方向上的逐渐连接。