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公开(公告)号：US20250124273A1
公开(公告)日：2025-04-17
申请号：US18930209
申请日：2024-10-29
Applicant: Rambus Inc.
Inventor： Dongyun Lee , Brent S. Haukness
Abstract: An integrated-circuit neural network includes chain of multiply-accumulate units co-located with a high-bandwidth storage array. Each multiply accumulate includes a digital input port, analog input port and multiply-adder circuitry. The digital input port receives a matrix of digital-weight values from the storage array and the analog input port receives a counterpart matrix of analog input signals, each analog input signal exhibiting a respective electronic current representative of input value. The multiply-adder circuitry generates a matrix of analog output signals by convolving the matrix of digital-weight values with the matrix of analog input signals including, for each analog output signal within the matrix of analog output signals, switchably enabling weighted current contributions to the analog output signal based on logic states of on respective bits of one or more of the digital-weight values.
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公开(公告)号：US12222829B2
公开(公告)日：2025-02-11
申请号：US18373219
申请日：2023-09-26
Applicant: Rambus Inc.
Inventor： Frederick A. Ware , Brent S. Haukness , John Eric Linstadt , Scott C. Best
IPC: G06F11/20 , G11C11/4093 , G11C29/52
Abstract: A memory module is disclosed. The memory module includes a substrate, and respective first, second and third memory devices. The first memory device is of a first type disposed on the substrate and has addressable storage locations. The second memory device is also of the first type, and includes storage cells dedicated to store failure address information associated with defective storage locations in the first memory device. The third memory device is of the first type and includes storage cells dedicated to substitute as storage locations for the defective storage locations.
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公开(公告)号：US12217784B2
公开(公告)日：2025-02-04
申请号：US17909940
申请日：2021-03-08
Applicant: Rambus Inc.
Inventor： Thomas Vogelsang , Brent S. Haukness
IPC: G11C11/4091 , G11C11/406 , G11C11/4094
Abstract: The dynamic memory array of a DRAM device is operated using at least two voltages. The first voltage, which is used to power the sense amplifiers during sense (i.e., read) operations and most other column operations (e.g., precharge, activate, write), is the operating (i.e., switching) voltage of a majority of the digital logic circuitry of the DRAM device. The second voltage, which determines the voltage written to the capacitor of the DRAM cells (i.e., bitline voltage) is greater than the operating (i.e., switching) voltage of a majority of the digital logic circuitry of the DRAM device. The digital logic circuitry is operated using a supply voltage that is lower than the voltage written to the capacitors of the DRAM array. This allows lower voltage swing digital logic to be used for a majority of the logic on the DRAM device while writing a larger voltage to the DRAM cells.
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公开(公告)号：US12165047B2
公开(公告)日：2024-12-10
申请号：US17424254
申请日：2020-01-23
Applicant: Rambus Inc.
Inventor： Dongyun Lee , Brent S. Haukness
Abstract: An integrated-circuit neural network includes chain of multiply-accumulate units co-located with a high-bandwidth storage array. Each multiply accumulate includes a digital input port, analog input port and multiply-adder circuitry. The digital input port receives a matrix of digital-weight values from the storage array and the analog input port receives a counterpart matrix of analog input signals, each analog input signal exhibiting a respective electronic current representative of input value. The multiply-adder circuitry generates a matrix of analog output signals by convolving the matrix of digital-weight values with the matrix of analog input signals including, for each analog output signal within the matrix of analog output signals, switchably enabling weighted current contributions to the analog output signal based on logic states of on respective bits of one or more of the digital-weight values.
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公开(公告)号：US11347608B2
公开(公告)日：2022-05-31
申请号：US16670798
申请日：2019-10-31
Applicant: Rambus Inc.
Inventor： Frederick A. Ware , Brent S. Haukness , John Eric Linstadt , Scott C. Best
IPC: G06F11/00 , G06F11/20 , G11C11/4093 , G11C29/52
Abstract: A memory module is disclosed. The memory module includes a substrate, and respective first, second and third memory devices. The first memory device is of a first type disposed on the substrate and has addressable storage locations. The second memory device is also of the first type, and includes storage cells dedicated to store failure address information associated with defective storage locations in the first memory device. The third memory device is of the first type and includes storage cells dedicated to substitute as storage locations for the defective storage locations.
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Patent Agency Ranking
公开(公告)号：US20220114431A1
公开(公告)日：2022-04-14
申请号：US17424254
申请日：2020-01-23
Applicant: Rambus Inc.
Inventor： Dongyun Lee , Brent S. Haukness
Abstract: An integrated-circuit neural network includes chain of multiply-accumulate units co-located with a high-bandwidth storage array. Each multiply accumulate includes a digital input port, analog input port and multiply-adder circuitry. The digital input port receives a matrix of digital-weight values from the storage array and the analog input port receives a counterpart matrix of analog input signals, each analog input signal exhibiting a respective electronic current representative of input value. The multiply-adder circuitry generates a matrix of analog output signals by convolving the matrix of digital-weight values with the matrix of analog input signals including, for each analog output signal within the matrix of analog output signals, switchably enabling weighted current contributions to the analog output signal based on logic states of on respective bits of one or more of the digital-weight values.
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公开(公告)号：US11226909B2
公开(公告)日：2022-01-18
申请号：US16546176
申请日：2019-08-20
Applicant: Rambus Inc.
Inventor： Liji Gopalakrishnan , Frederick A. Ware , Brent S. Haukness
Abstract: Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, an integrated circuit (IC) memory device is disclosed. The memory device includes an array of storage cells and command interface circuitry to receive an internal transfer command. In response to the internal transfer command, transfer logic reads data from a first portion of the array of storage cells, transfers the data as on-chip transfer data, and writes the on-chip transfer data to a second portion of the array of storage cells. In response to the command interface circuitry receiving an interrupt command, the transfer logic pauses the internal transfer operation, and carries out an unrelated memory access operation involving at least the first portion of the array of storage cells or the second portion of the array of storage cells.
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公开(公告)号：US20210133061A1
公开(公告)日：2021-05-06
申请号：US16670798
申请日：2019-10-31
Applicant: Rambus Inc.
Inventor： Frederick A. Ware , Brent S. Haukness , John Eric Linstadt , Scott C. Best
IPC: G06F11/20 , G11C29/52 , G11C11/4093
Abstract: A memory module is disclosed. The memory module includes a substrate, and respective first, second and third memory devices. The first memory device is of a first type disposed on the substrate and has addressable storage locations. The second memory device is also of the first type, and includes storage cells dedicated to store failure address information associated with defective storage locations in the first memory device. The third memory device is of the first type and includes storage cells dedicated to substitute as storage locations for the defective storage locations.
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公开(公告)号：US10658037B2
公开(公告)日：2020-05-19
申请号：US16209479
申请日：2018-12-04
Applicant: RAMBUS INC.
Inventor： Deepak Chandra Sekar , Brent S. Haukness , Bruce L. Bateman
Abstract: A memory device may include a local bit line electrically coupled to a plurality of memory cells and a global bit line electrically coupled to the local bit line through first and second selectable parallel paths having first and second impedances, respectively. The first path may be active and the second path may be in an off state in at least one of a set operation or a forming operation. The second path may be active in a reset operation, wherein the second impedance of the second path has a lower impedance than the first impedance of the first path.
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公开(公告)号：US20200065268A1
公开(公告)日：2020-02-27
申请号：US16546176
申请日：2019-08-20
Applicant: Rambus Inc.
Inventor： Liji Gopalakrishnan , Frederick A. Ware , Brent S. Haukness
Abstract: Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, an integrated circuit (IC) memory device is disclosed. The memory device includes an array of storage cells and command interface circuitry to receive an internal transfer command. In response to the internal transfer command, transfer logic reads data from a first portion of the array of storage cells, transfers the data as on-chip transfer data, and writes the on-chip transfer data to a second portion of the array of storage cells. In response to the command interface circuitry receiving an interrupt command, the transfer logic pauses the internal transfer operation, and carries out an unrelated memory access operation involving at least the first portion of the array of storage cells or the second portion of the array of storage cells.
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