Abstract:
A light emitting device circuit has one or plural light emitting devices connected in series. A light emitting device driver circuit drives the light emitting device circuit according to a rectified input voltage. The light emitting device driver circuit includes a power switch and a control circuit. When the power switch is conductive, a light emitting device current flows through the light emitting device circuit and the power switch. When the power switch is not conductive, an output capacitor discharges to provide the light emitting device current. The control circuit determines whether the rectified input voltage is lower or not lower than a forward voltage plus a reference voltage according to a voltage at a reverse end of the light emitting device circuit, and control the power switch accordingly.
Abstract:
A mixed mode compensation circuit for a power converter generate a digital signal according to a reference signal and a feedback signal which is related to the output voltage of the power converter, convert the digital signal into a first analog signal, offset the first analog signal with a variable offset value to generate a second analog signal, and filter out high-frequency components of the second analog signal to generate a third analog signal for stable output voltage of the power converter. The mixed mode compensation does not require large capacitors, and thus the circuit can be integrated into an integrated circuit.
Abstract:
An LED control device for configuring a phase-cut dimming system includes an LED and a switch. The LED control device configures the conduction status of the switch so as to supply power to the LED according to an input signal. The LED control device further detects whether the input signal is phase-cut. When the input signal is phase-cut, the LED control device stores the signal values of the internal circuits. Afterward, when the input signal is not phase-cut, the LED control device restores the stored signal values so that the internal circuits may resume to the previous operation status rapidly.
Abstract:
A floating gate driver uses a single-end level shifter to translate a set signal and a reset signal induced by a rising edge and a falling edge of a switch signal to a common output terminal to generate an output voltage for a bistable circuit to generate a level shifted switch signal. Under control of a well transient detect signal asserted by detecting noise in the output voltage, a masking circuit between the single-end level shifter and the bistable circuit masks noise in the output voltage. This configuration has lower area penalty and better noise immunity.
Abstract:
An output stage circuit for transmitting data via a bus includes a high side switch, a high side diode structure, a high side clamp circuit, a low side switch, and a low side diode structure. An impedance circuit of the bus is coupled between the high side switch and the low side switch, for generating a differential output signal according to high and low side output signals. A high side N-type region of the high side diode structure encompasses a high side P-type region thereof, and a low side N-type region of the low side diode structure encompasses a low side P-type region thereof. The high side clamp circuit is connected to the high side N-type region in series, for clamping a voltage of the high side N-type region to be not lower than a predetermined voltage, to prevent a parasitic PNP bipolar junction transistor from being turned ON.
Abstract:
An output stage circuit for transmitting data via a bus includes a high side switch, a high side diode structure, a high side clamp circuit, a low side switch, and a low side diode structure. An impedance circuit of the bus is coupled between the high side switch and the low side switch, for generating a differential output signal according to high and low side output signals. A high side N-type region of the high side diode structure encompasses a high side P-type region thereof, and a low side N-type region of the low side diode structure encompasses a low side P-type region thereof. The high side clamp circuit is connected to the high side N-type region in series, for clamping a voltage of the high side N-type region to be not lower than a predetermined voltage, to prevent a parasitic PNP bipolar junction transistor from being turned ON.
Abstract:
Whether a synchronous signal includes a synchronous pulse is determined by detecting whether there is a positive pulse higher than a positive threshold followed by a negative pulse lower than a negative threshold. The pulse signal detection method includes: comparing the synchronous signal with the positive threshold; comparing the synchronous signal with the negative threshold; and determining that the synchronous pulse exists when the positive pulse of the synchronous signal is higher than the positive threshold and the negative pulse of the synchronous signal is lower than the negative threshold in a post detection period after the positive pulse of the synchronous signal is determined higher than the positive threshold.
Abstract:
A transmission interface with noise reduction function includes a first circuit and a second circuit, for transmitting a signal from the first circuit to the second circuit or from the second circuit to the first circuit. The first circuit includes a first sub-winding and a first wire unit, and the second circuit includes a second sub-winding and a second wire unit. When an electromagnetic noise passes through the first sub-winding and the first wire unit, two loop currents are respectively generated, and the currents have opposite directions to cancel each other so as to reduce the electromagnetic noise. Or, when an emitting current corresponding to the signal flows through the first sub-winding and the first wire unit, two magnetic fields are respectively generated, and the magnetic fields have opposite directions to cancel each other so as to reduce the electromagnetic interference.
Abstract:
The present invention discloses a short circuit and/or bad connection detection method for use in a power supply system. The power supply system includes a power converter which converts an input voltage to an output voltage and supplies an output current to an electronic device. In the short circuit detection method, the conversion from the input voltage to the output voltage is disabled in a disable time period, and whether a short circuit occurs is determined according to the decreasing speed of the output voltage. In the bad connection detection method, an actual voltage and an actual current received by the electronic device are compared with the output voltage and the output current, to determine whether a bad connection occurs.
Abstract:
A buck switching regulator includes: a power stage, which includes: an upper-gate switch, a lower-gate switch and an inductor, connected with one another at a switching node; and a supply control switch, controlling the power supply form an output terminal to a load. An overvoltage protection method includes the following steps: (A) sensing a voltage of the switching node, to obtain a switching node voltage; (B) determining whether an overvoltage event occurs in the switching node voltage; and (C) if it is determined yes in the step (B), outputting a protection signal. An overvoltage event is determined directly according to the switching node voltage, not directly according to the output voltage.