公开(公告)号：US10811532B2

公开(公告)日：2020-10-20

申请号：US16352795

申请日：2019-03-13

Applicant: RICHTEK TECHNOLOGY CORPORATION

Inventor： Tsung-Yi Huang ,  Chien-Yu Chen

IPC: H01L29/78 ,  H01L29/10 ,  H01L21/762 ,  H01L29/06 ,  H01L29/66

Abstract: A high voltage device includes: a semiconductor layer, an isolation structure, a drift oxide region, a well, a body region, a body contact, a buffer region, a gate, and a source and a drain. The body contact includes a main body contact and at least one sub-body contact. The main body contact is adjacent to the source, wherein the main body contact and the source are rectangles that extend along a width direction, and the source is located between the main body contact and the gate. The sub-body contact extends from the main body contact toward the gate and contacts an inverse current channel. The buffer region encompasses all the periphery of the body region below a top surface of the semiconductor layer, wherein an impurity concentration of the buffer region is lower than an impurity concentration of the body region.

公开(公告)号：US20200212207A1

公开(公告)日：2020-07-02

申请号：US16668327

申请日：2019-10-30

Applicant: RICHTEK TECHNOLOGY CORPORATION

Inventor： Tsung-Yi Huang

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/10 ,  H01L29/808 ,  H01L21/265 ,  H01L21/762

Abstract: A manufacturing method of a junction field effect transistor (JFET) includes: providing a substrate having a first conductivity type, forming a channel region having a second conductive type, forming a field region having the first conductivity type, forming a gate having the first conductivity type, forming a source having the second conductive type, forming a drain having the second conductive type, and forming a lightly doped region having the second conductive type. The channel region is formed by a first ion implantation process step, and the lightly doped region is formed by a second ion implantation process step. The second ion implantation process step implants first conductivity type impurities into a part of the channel region.

公开(公告)号：US20190378924A1

公开(公告)日：2019-12-12

申请号：US16352795

申请日：2019-03-13

Applicant: RICHTEK TECHNOLOGY CORPORATION

Inventor： Tsung-Yi Huang ,  Chien-Yu Chen

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/66 ,  H01L29/06 ,  H01L21/762

Abstract: A high voltage device includes: a semiconductor layer, an isolation structure, a drift oxide region, a well, a body region, a body contact, a buffer region, a gate, and a source and a drain. The body contact includes a main body contact and at least one sub-body contact. The main body contact is adjacent to the source, wherein the main body contact and the source are rectangles that extend along a width direction, and the source is located between the main body contact and the gate. The sub-body contact extends from the main body contact toward the gate and contacts an inverse current channel. The buffer region encompasses all the periphery of the body region below a top surface of the semiconductor layer, wherein an impurity concentration of the buffer region is lower than an impurity concentration of the body region.

公开(公告)号：US20190341491A1

公开(公告)日：2019-11-07

申请号：US16232030

申请日：2018-12-25

Applicant: RICHTEK TECHNOLOGY CORPORATION

Inventor： Tsung-Yi Huang

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/08

Abstract: A high voltage device includes: a semiconductor layer, an isolation structure, a drift oxide region, a well, a body region, a gate, at least one sub-gate, a source, a drain and a conductive connection structure. The drift oxide region is located on a drift region in an operation region. The sub-gate is formed on the drift oxide region in the operation region. The sub-gate is a rectangle shape extending along a width direction, and in parallel with the gate. A conductive connection structure connects the gate and the sub-gate.

公开(公告)号：US10355088B2

公开(公告)日：2019-07-16

申请号：US15622227

申请日：2017-06-14

Applicant: RICHTEK TECHNOLOGY CORPORATION

Inventor： Tsung-Yi Huang ,  Ying-Shiou Lin

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L21/74 ,  H01L29/08 ,  H01L29/66

Abstract: The present invention provides a MOS (Metal-Oxide-Silicon) device having mitigated threshold voltage roll-off and a threshold voltage roll-off mitigation method therefor. The MOS device includes: a substrate, a well region, an isolation region, a gate, two LDDs (Lightly-Doped-Drains), a source, a drain and a compensation doped region. The compensation doped region is substantially in contact with at least a part of a recessed portion along the channel length direction. Viewing from a cross-section view, at a boundary where the compensation doped region is in contact with the isolation region along the channel length direction, the compensation doped region has two doped region widths along the channel width direction, wherein, the two doped region widths of the compensation doped region are both not greater than 10% of the width of the operation region. Two doped region widths are defined as distances within an interior part and an exterior part of the operation region, respectively.

公开(公告)号：US20190181253A1

公开(公告)日：2019-06-13

申请号：US16278698

申请日：2019-02-18

Applicant: RICHTEK TECHNOLOGY CORPORATION

Inventor： Kuo-Hsuan Lo ,  Tsung-Yi Huang

IPC: H01L29/739 ,  H01L29/06 ,  H01L29/78 ,  H01L29/423

CPC classification number: H01L29/7395 ,  H01L29/0619 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/782 ,  H01L29/7835 ,  H01L29/872

Abstract: The invention provides a power device, which includes: an operation layer, including a top surface, a body region and a drift region, the body region and the drift region being connected in a lateral direction, to form a PN junction along a channel width direction between the body region and the drift region; a gate, formed on the top surface, and the PN junction is located under the gate; a source, formed in a portion of the operation layer between the body region and the top surface; a drain, formed in another portion of the operation layer between the drift region and the top surface; a first conduction portion, formed on the top surface for electrically connecting the source; a conduction layer, formed on the first conduction portion and electrically connected to the source via the first conduction portion; and a second conduction portion, formed on the top surface and between the conduction layer and the drift region in a thickness direction, for electrically connecting the drift region and the conduction layer, wherein a Schottky diode is formed by the second conduction portion and the drift region.

公开(公告)号：US20190115468A1

公开(公告)日：2019-04-18

申请号：US16104921

申请日：2018-08-19

Applicant: RICHTEK TECHNOLOGY CORPORATION

Inventor： Tsung-Yi Huang ,  Chu-Feng Chen ,  Yu-Ting Yeh

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/08 ,  H01L29/66 ,  H01L21/266

Abstract: A high voltage MOS device includes: a well, a body region, a gate, a source, plural body contact regions and a drain. The plural body contact regions are formed in the body region, wherein each of the body contact region is located beneath the top surface and contacts the top surface in the vertical direction, and is in contact or not in contact with the gate in the lateral direction. The plural body contact regions are arranged substantially in parallel in the width direction and any two neighboring body contact regions are not in contact with each other in the width direction. The gate includes a poly-silicon layer which serves as the only electrical contact of the gate, and every part of the poly-silicon layer is the first conductivity type.

公开(公告)号：US20190043985A1

公开(公告)日：2019-02-07

申请号：US16158261

申请日：2018-10-11

Applicant: RICHTEK TECHNOLOGY CORPORATION

Inventor： Tsung-Yi Huang

IPC: H01L29/78 ,  H01L21/768 ,  H01L29/66 ,  H01L23/535 ,  H01L29/06

Abstract: The present invention provides a MOS (Metal-Oxide-Silicon) device and a manufacturing method thereof. The MOS device includes: a semiconductor substrate, a gate, a source, a drain, and two LDDs (Lightly-Doped-Drains). At least one recess is formed at an upper surface of the semiconductor substrate. The recess has a depth which is deeper than the depth of the two LDDs. The recess is filled with a conductive material. A vertical connection portion is formed at a boundary of the recess in the vertical direction, to at least connect one of the LDDs to the drain. The LDD closer to the drain is not laterally in contact with the drain but is connected to the drain by the vertical direction.

公开(公告)号：US20180350903A1

公开(公告)日：2018-12-06

申请号：US15662277

申请日：2017-07-27

Applicant: RICHTEK TECHNOLOGY CORPORATION

Inventor： Tsung-Yi Huang ,  Chu-Feng Chen

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/10 ,  H01L29/40 ,  H01L21/265 ,  H01L21/266 ,  H01L21/324 ,  H01L21/225 ,  H01L29/66

CPC classification number: H01L29/0634 ,  H01L21/2253 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/324 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/408 ,  H01L29/66681 ,  H01L29/7816

Abstract: A high voltage MOS device includes: a first drift region with a first conductive type, a body region with a second conductive type, plural second drift regions with the second conductive type, a gate, a source region with the first conductive type, a drain with the first conductive type, and a body contact region with the second conductive type. The plural second drift regions contact the body region along the lateral direction, and are located separately in the width direction. Any neighboring two second drift regions do not contact each other. Each of the second drift regions is separated from the drain by the first drift region.

公开(公告)号：US20180337276A1

公开(公告)日：2018-11-22

申请号：US15937741

申请日：2018-03-27

Applicant: RICHTEK TECHNOLOGY CORPORATION

Inventor： Tsung-Yi Huang

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/40 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66

CPC classification number: H01L29/7823 ,  H01L21/26513 ,  H01L21/266 ,  H01L29/0649 ,  H01L29/086 ,  H01L29/0865 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/66681 ,  H01L29/66689 ,  H01L29/66704 ,  H01L29/7825 ,  H01L29/7835

Abstract: The present invention discloses a high voltage device and a manufacturing method thereof. The high voltage device is formed in a semiconductor substrate, and includes: a gate, a source, a drain, and at least one plug plate electrode. The plug plate electrode is in direct contact with the gate, and is electrically connected to the gate. The plug plate electrode extends downwards from the bottom of the gate to the semiconductor substrate, through a current vertical height of a conductive current when the high voltage is ON. The plug plate electrode is between the source and the drain in a lateral direction. The plug plate electrode includes a dielectric layer and a conductive layer.