摘要:
A variable number of parity bits or error correction code per word is used to increase error detection for words having the extra parity bits in a control store. Since some words do not utilize all the architected space available for words, extra parity bits are generated at development time for such words and stored with the words. A decoder identifies the location and number of parity bits. Parity checking against the extra parity bits is then performed on different groups of bits in the word. This provides an inexpensive means of increasing error detection with minimal hardware cost.
摘要:
Mechanisms are provided for extending cache for an external storage system into individual servers. Certain servers may have cards with cache in the form of dynamic random access memory (DRAM) and non-volatile storage, such as flash memory or solid-state drives (SSDs), which may be viewed as actual extensions of the external storage system. In this way, the storage system is distributed across the storage area network (SAN) into various servers. Several new semantics are used in communication between the cards and the storage system to keep the read caches coherent.
摘要:
Mechanisms for managing data segments in a tiered storage system are provided. The mechanisms maintain at least one counter for each data segment in the tiered storage system. Each counter in the at least one counter counts a number of access operations to a corresponding data segment for a predetermined time interval. The mechanisms further perform one or more analytical operations based on one or more values of the at least one counter for each data segment to make residence determinations for each data segment. The mechanisms also adjust a storage location of one or more data segments in tiers of the tiered storage system to thereby move the one or more data segments to appropriate tiers of the tiered storage system based on results of the one or more analytical operations.
摘要:
A mechanism is provided for enabling throttling on average write throughput instead of peak write throughput for solid-state storage devices. The mechanism assures an average write throughput within a range but allows excursions of high throughput with periods of low throughput offsetting against those of heavy usage. The mechanism periodically determines average throughput and determines whether average throughput exceeds a high throughput threshold for a certain amount of time without being offset by periods of low throughput.
摘要:
A storage device is provided for direct memory access. A controller of the storage device performs a mapping of a window of memory addresses to a logical block addressing (LBA) range of the storage device. Responsive to receiving from a host a write request specifying a write address within the window of memory addresses, the controller initializes a first memory buffer in the storage device and associates the first memory buffer with a first address range within the window of memory addresses such that the write address of the request is within the first address range. The controller writes to the first memory buffer based on the write address. Responsive to the buffer being full, the controller persists contents of the first memory buffer to the storage device using logical block addressing based on the mapping.
摘要:
A mechanism is provided for enabling throttling on average write throughput instead of peak write throughput for solid-state storage devices. The mechanism assures an average write throughput within a range but allows excursions of high throughput with periods of low throughput offsetting against those of heavy usage. The mechanism periodically determines average throughput and determines whether average throughput exceeds a high throughput threshold for a certain amount of time without being offset by periods of low throughput.
摘要:
Mechanisms for storing data to a storage system comprising a set of one or more solid state storage devices and a set of non-solid state storage devices are provided. A request to write data to the storage system is received and the data is written to the set of one or more solid state storage devices in response to receiving the request. Moreover, a mirror copy of the data is written to the set of non-solid state storage devices in response to receiving the request. Thus, the non-solid state storage devices serve as a mirror backup copy of the data stored to the solid state storage devices.
摘要:
A redundant and fault tolerant solid state disk (SSD) includes a determination module configured to identify a first solid state disk controller (SSDC) configured to connect to a flash array and a second SSDC configured to connect to the flash array. A capture module is configured to capture a copy of an I/O request received by the first SSDC from a port of a dual port connector, and/or capture a copy of an I/O request received by the second SSDC from a port of the dual port connector, and identify a write I/O request from the I/O request. A detection module is configured to detect a failure in the first SSDC. A management module is configured to manage access to a flash array by the first SSDC and the second SSDC. An error recovery and failover module is configured to automatically reassign work from the first SSDC to the second SSDC.
摘要:
Mechanisms for managing data segments in a tiered storage system are provided. The mechanisms maintain at least one counter for each data segment in the tiered storage system. Each counter in the at least one counter counts a number of access operations to a corresponding data segment for a predetermined time interval. The mechanisms further perform one or more analytical operations based on one or more values of the at least one counter for each data segment to make residence determinations for each data segment. The mechanisms also adjust a storage location of one or more data segments in tiers of the tiered storage system to thereby move the one or more data segments to appropriate tiers of the tiered storage system based on results of the one or more analytical operations.
摘要:
A method, apparatus and program storage device for providing self-quiesced logic for handling an error recovery instruction such as a reset or self-test instruction. For example, during a reset or self test procedure, the logic is isolated without adversely affecting the local processor. Self-quiesced logic processes an error recovery instruction by monitoring the processor interface for an idle condition and withholding access to the local processor. Once the local processor interface has been quiesced and the internal logic paths are idle, the logic will proceed with the reset or self-test.