公开(公告)号：US5831917A

公开(公告)日：1998-11-03

申请号：US884854

申请日：1997-06-30

申请人： Joerg Vollrath

发明人： Joerg Vollrath

IPC分类号： G11C11/413 ,  G11C11/401 ,  G11C29/00 ,  G11C29/04 ,  G11C7/00

CPC分类号： G11C29/787

摘要： A memory array having a first plurality of fuse-sharing redundant elements for replacing defective elements of the memory array. The memory array includes a first fuse, and first group of redundant elements of the first plurality of fuse-sharing redundant elements. The first group of redundant elements share the first fuse as their highest order address fuse. The memory array further includes a second group of redundant elements of the first plurality of fuse-sharing redundant elements. The second group of redundant elements is mutually exclusive with respect to the first group of redundant elements.

摘要翻译： 一种存储器阵列，具有用于替换存储器阵列的有缺陷元件的第一多个熔丝共享冗余元件。 存储器阵列包括第一熔丝和第一组多个熔丝共享冗余元件的第一组冗余元件。 第一组冗余元件共享第一个保险丝作为其最高级地址保险丝。 存储器阵列还包括第一组多个熔丝共享冗余元件的第二组冗余元件。 第二组冗余元件与第一组冗余元件相互排斥。

公开(公告)号：US20080180983A1

公开(公告)日：2008-07-31

申请号：US12021750

申请日：2008-01-29

申请人： Joerg Vollrath

发明人： Joerg Vollrath

IPC分类号： G11C17/00

CPC分类号： G11C17/14 ,  G11C17/143 ,  G11C17/16 ,  G11C17/18 ,  G11C29/028 ,  G11C29/70 ,  G11C2229/763 ,  G11C2229/766

摘要： A semiconductor device and method with a plurality of different one time programmable elements. One embodiment provides a semiconductor device having a plurality of different one time programmable elements that form a group of one time programmable elements, wherein at least one bit of information is jointly stored by the plurality of different one time programmable elements of the group.

摘要翻译： 一种具有多个不同的一次可编程元件的半导体器件和方法。 一个实施例提供了具有多个不同的一次可编程元件的半导体器件，其形成一组一次可编程元件，其中由该组的多个不同的一次可编程元件共同存储至少一个位的信息。

公开(公告)号：US20060049469A1

公开(公告)日：2006-03-09

申请号：US11213342

申请日：2005-08-26

申请人： Joerg Vollrath

发明人： Joerg Vollrath

IPC分类号： H01L29/76

CPC分类号： H01L27/11568 ,  H01L27/115 ,  H01L29/66833

摘要： An integrated semiconductor circuit includes a transistor and a strip conductor (11). The transistor includes a first (1) and a second source/drain region (2) and a gate electrode. The strip conductor (11) is electrically insulated from a semiconductor body at least by a gate dielectric and forms the gate electrode in the area of the transistor. The strip conductor (11) extends along a first direction (x) in the area of the transistor. The second source/drain region (2) is arranged offset with respect to the first source/drain region (1) in the first direction (x). The transistor thus formed has an inversion channel (K1) that only extends between two corner areas (1a, 2a) facing one another of the first and of the second source/drain region, i.e. is much narrower than in the case of a conventional transistor.

摘要翻译： 集成半导体电路包括晶体管和带状导体（11）。 晶体管包括第一（1）和第二源/漏区（2）和栅电极。 带状导体（11）至少通过栅极电介质与半导体本体电绝缘，并在晶体管的区域中形成栅电极。 带状导体（11）沿着晶体管的区域中的第一方向（x）延伸。 第二源极/漏极区域（2）在第一方向（x）上相对于第一源极/漏极区域（1）偏移地布置。 这样形成的晶体管具有仅在第一和第二源极/漏极区域彼此面对的两个拐角区域（1a，2a）之间延伸的反转沟道（K 1），即比在 常规晶体管。

公开(公告)号：US06981175B2

公开(公告)日：2005-12-27

申请号：US09967008

申请日：2001-09-28

申请人： Joerg Vollrath ,  Philip Moore

发明人： Joerg Vollrath ,  Philip Moore

IPC分类号： G06F11/00 ,  G06F11/10 ,  G06F11/16 ,  G06F12/02 ,  G11C29/00 ,  G11C29/02 ,  G11C29/42 ,  H04L1/22

CPC分类号： G06F11/1004 ,  G11C29/02 ,  G11C29/027 ,  G11C29/42 ,  G11C29/785

摘要： A memory includes: a memory array having a plurality of storage elements; a plurality of replacement storage elements; a plurality of address fuse units, each having a plurality of fusible links and being operable to store a replacement address, each replacement address identifying one of the storage elements of the memory array to be replaced by an associated one of the replacement storage elements and forming a respective 2m bit row or 2n bit column of a fuse array; a vector generator operable to produce a 2n bit row vector based on the rows of the fuse array and to produce a 2m bit column vector based on the columns of the fuse array; and a compression unit operable to produce a row checksum from the row vector and to produce a column checksum from the column vector.

摘要翻译： 存储器包括：具有多个存储元件的存储器阵列; 多个替换存储元件; 多个地址熔丝单元，每个地址熔丝单元具有多个可熔链，并且可操作以存储替换地址，每个替换地址标识存储器阵列的存储元件之一，以被相关联的一个替换存储元件代替并形成 保险丝阵列的相应的2 比特列或2 比特列; 矢量发生器，其可操作以基于所述保险丝阵列的行产生2位比特行向量，并且基于所述保险丝的列产生2比特列向量 阵列 以及压缩单元，其可操作以从所述行向量产生行校验和，并从所述列向量产生列校验和。

公开(公告)号：US06816094B2

公开(公告)日：2004-11-09

申请号：US10619290

申请日：2003-07-15

申请人： Joerg Vollrath ,  Stephan Schröder

发明人： Joerg Vollrath ,  Stephan Schröder

IPC分类号： H03M900

CPC分类号： G11C7/1057 ,  G11C7/1051

摘要： A circuit configuration for the bit-parallel outputting the bits of a data word includes at least two signal lines for feeding the data signals representing the bits of the data word to driver stages and to a reference circuit. Further driver stages are connected in parallel with the driver stages and have inputs connected to the control device. The control device establishes the signal states of the data signals to be transferred on each signal line and generates a control signal depending on the type and number of the signal state changes of bit sequences to be transferred. It is possible to drive the driver stages that assigned to the signal line for which a signal state change is present.

摘要翻译： 用于比特并行输出数据字的位的电路配置包括用于将表示数据字的位的数据信号馈送到驱动器级的至少两条信号线和参考电路。 其他驱动级与驱动级并联，并具有连接到控制装置的输入。 控制装置建立要在每个信号线上传送的数据信号的信号状态，并根据要传送的位序列的信号状态变化的类型和数量产生控制信号。 可以驱动分配给信号状态改变的信号线的驱动级。

公开(公告)号：US06564346B1

公开(公告)日：2003-05-13

申请号：US09455855

申请日：1999-12-07

申请人： Joerg Vollrath ,  Ulf Lederer ,  Peter Oswald ,  Thomas Hladschik ,  Zschunke Andreas ,  Rausch Harold

发明人： Joerg Vollrath ,  Ulf Lederer ,  Peter Oswald ,  Thomas Hladschik ,  Zschunke Andreas ,  Rausch Harold

IPC分类号： G11C2900

CPC分类号： G11C29/72 ,  G01R31/31935 ,  G11C29/56

摘要： A method for providing a compressed bit fail map, in accordance with the invention includes the steps of testing a semiconductor device to determine failed devices and transferring failure information to display a compressed bit map by designating areas of the bit map for corresponding failure locations on the semiconductor device. Failure classification is provided by designating shapes and dimensions of fail areas in the designated areas of the bit map such that the fail area shapes and dimensions indicate a fail type.

摘要翻译： 根据本发明的用于提供压缩比特失败映射的方法包括以下步骤：测试半导体器件以确定故障设备并传送故障信息以显示压缩位图，通过指定位图上的相应故障位置的区域 半导体器件。 通过在位图的指定区域中指定失效区域的形状和尺寸来提供故障分类，使得故障区域形状和尺寸表示故障类型。

公开(公告)号：US06453433B1

公开(公告)日：2002-09-17

申请号：US09281021

申请日：1999-03-30

申请人： Joerg Vollrath

发明人： Joerg Vollrath

IPC分类号： G11C2900

CPC分类号： G11C29/028 ,  G11C11/401 ,  G11C29/02 ,  G11C29/50 ,  G11C2029/5004

摘要： Disclosed is a method and apparatus for testing a semiconductor memory having a plurality of memory cells arranged in rows and columns and a plurality of sense amplifiers, each for amplifying memory cell signals of a common row or column. In an illustrative embodiment of the method, a voltage level or test pattern is written into at least one target cell of the memory cells. A word line coupled to the target cell is then activated and subsequently deactivated, to thereby modify the voltage level stored in the cell, while the associated sense amplifier is prevented from refreshing the cell as the word line is activated, e.g., by disabling the sense amplifier. A test bit line voltage is then applied to a bit line coupled to the cell to charge the same. Data is then read from the target cell with settings of the associated sense amplifier enabled, and compared to the original voltage level written into the cell. The process is repeated for different test bit line voltages. The method can be used to determine the signals at the sense amplifiers during normal operation of the memory, without employing complex and costly picoprobes.

摘要翻译： 公开了一种用于测试半导体存储器的方法和装置，该半导体存储器具有排列成行和列的多个存储单元和多个读出放大器，每个用于放大公共行或列的存储单元信号。 在该方法的说明性实施例中，将电压电平或测试图案写入存储器单元的至少一个目标单元。 然后，耦合到目标单元的字线被激活并且随后被去激活，从而修改存储在单元中的电压电平，同时当字线被激活时防止相关的读出放大器刷新单元，例如通过禁用该感测 放大器 然后将测试位线电压施加到耦合到该单元的位线以对其进行充电。 然后从相关读出放大器的设置使能的目标单元读取数据，并将其与写入单元的原始电压电平进行比较。 针对不同的测试位线电压重复该过程。 该方法可用于在存储器的正常操作期间确定读出放大器处的信号，而不需要使用复杂和昂贵的皮秒。

公开(公告)号：US07719868B2

公开(公告)日：2010-05-18

申请号：US11715839

申请日：2007-03-08

申请人： Joerg Vollrath

发明人： Joerg Vollrath

IPC分类号： G11C5/06

CPC分类号： G11C5/063 ,  G11C7/18 ,  G11C11/4097 ,  H01L27/10885 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated semiconductor memory has memory cells, with at least one pair of bit lines which comprises a first bit line and a second bit line, and with at least one sense amplifier which has the first bit line and the second bit line connected to it. The bit lines respectively have a first conductor track structure and a second conductor track structure, where the memory cells are respectively connected to the second conductor track structure, and where the first conductor track structure is respectively interposed between the sense amplifier and the second conductor track structure of the respective bit line and is arranged at a greater distance from the substrate area than the respective second conductor track structure.

摘要翻译： 集成半导体存储器具有存储单元，其中至少一对位线包括第一位线和第二位线，以及至少一个读出放大器，其具有与其连接的第一位线和第二位线。 位线分别具有第一导体轨道结构和第二导体轨道结构，其中存储单元分别连接到第二导体轨道结构，并且其中第一导体轨道结构分别插入在读出放大器和第二导体轨道之间 相对于位线的结构，并且布置在距离基板区域比相应的第二导体轨道结构更远的距离处。

公开(公告)号：US07372095B2

公开(公告)日：2008-05-13

申请号：US11213342

申请日：2005-08-26

申请人： Joerg Vollrath

发明人： Joerg Vollrath

IPC分类号： H01L29/76 ,  H01L29/788

CPC分类号： H01L27/11568 ,  H01L27/115 ,  H01L29/66833

摘要： An integrated semiconductor circuit includes a transistor and a strip conductor (11). The transistor includes a first (1) and a second source/drain region (2) and a gate electrode. The strip conductor (11) is electrically insulated from a semiconductor body at least by a gate dielectric and forms the gate electrode in the area of the transistor. The strip conductor (11) extends along a first direction (x) in the area of the transistor. The second source/drain region (2) is arranged offset with respect to the first source/drain region (1) in the first direction (x). The transistor thus formed has an inversion channel (K1) that only extends between two corner areas (1a, 2a) facing one another of the first and of the second source/drain region, i.e. is much narrower than in the case of a conventional transistor.

摘要翻译： 集成半导体电路包括晶体管和带状导体（11）。 晶体管包括第一（1）和第二源/漏区（2）和栅电极。 带状导体（11）至少通过栅极电介质与半导体本体电绝缘，并在晶体管的区域中形成栅电极。 带状导体（11）沿着晶体管的区域中的第一方向（x）延伸。 第二源极/漏极区域（2）在第一方向（x）上相对于第一源极/漏极区域（1）偏移地布置。 这样形成的晶体管具有仅在第一和第二源极/漏极区域彼此面对的两个拐角区域（1a，2a）之间延伸的反转沟道（K 1），即比在 常规晶体管。

公开(公告)号：US06998664B2

公开(公告)日：2006-02-14

申请号：US10787119

申请日：2004-02-27

申请人： Joerg Vollrath ,  Stephan Schröder ,  Tobias Hartner

发明人： Joerg Vollrath ,  Stephan Schröder ,  Tobias Hartner

IPC分类号： H01L27/108 ,  H01L29/76

CPC分类号： H01L27/10885 ,  H01L27/10888 ,  H01L27/10891

摘要： An integrated semiconductor circuit includes a cell array having memory cells which can be read by word lines and bit lines. Two bit lines in each case are connected to inputs of the same signal amplifier. In order to compensate for parasitic capacitances which arise at thin sidewall insulations between the patterned word lines and adjacent bit line contacts which connect the bit lines located at a higher level to the active regions located at a deeper level, two additional word lines and dummy contacts of the bit lines are dummy contacts lead past this additional word lines. The additional parasitic capacitances produced by the dummy contacts alter the electrical potential of the respective reference bit line at the signal amplifier in the same way as the parasitic capacitances of activated bit lines, as a result of which the measured differential potential is corrected with respect to the parasitic effects.

摘要翻译： 集成半导体电路包括具有可由字线和位线读取的存储单元的单元阵列。 每种情况下的两个位线连接到相同信号放大器的输入。 为了补偿在图案化字线和相邻位线触点之间的薄侧壁绝缘处产生的寄生电容，其将位于较高电平的位线连接到位于较深电平的有源区，两个附加字线和虚拟触点 的位线是虚拟触点通过这个附加字线。 由虚拟触点产生的附加寄生电容以与激活的位线的寄生电容相同的方式改变信号放大器处的各个参考位线的电位，结果是相对于 寄生效应。