公开(公告)号：US20130070530A1

公开(公告)日：2013-03-21

申请号：US13622045

申请日：2012-09-18

申请人： Jian Chen ,  Sergei Gorobets ,  Steven Sprouse ,  Tien-Chien Kuo ,  Yan Li ,  Seungpil Lee ,  Alex Mak ,  Deepanshu Dutta ,  Masaaki Higashitani

发明人： Jian Chen ,  Sergei Gorobets ,  Steven Sprouse ,  Tien-Chien Kuo ,  Yan Li ,  Seungpil Lee ,  Alex Mak ,  Deepanshu Dutta ,  Masaaki Higashitani

IPC分类号： G11C16/04

CPC分类号： G11C16/10 ,  G11C5/063 ,  G11C11/5628 ,  G11C2211/5641

摘要： A non-volatile storage system is disclosed that includes non-volatile memory cells designed for high endurance and lower retention than other non-volatile memory cells.

摘要翻译： 公开了一种非易失性存储系统，其包括设计用于高耐久性和比其他非易失性存储器单元更低保持性的非易失性存储器单元。

公开(公告)号：US20110126080A1

公开(公告)日：2011-05-26

申请号：US12839237

申请日：2010-07-19

申请人： Jun Wan ,  Alex Mak ,  Tien-Chien Kuo ,  Yan Li ,  Jian Chen

发明人： Jun Wan ,  Alex Mak ,  Tien-Chien Kuo ,  Yan Li ,  Jian Chen

IPC分类号： G06F12/02 ,  H03M13/05 ,  G06F11/10

CPC分类号： G11C11/5642 ,  G11C11/5628 ,  G11C29/00

摘要： Non-volatile storage devices and techniques for operating non-volatile storage are described herein. One embodiment includes accessing “n” pages of data to be programmed into a group of non-volatile storage elements. The “n” pages are mapped to a data state for each of the non-volatile storage elements based on a coding scheme that evenly distributes read errors across the “n” pages of data. Each of the non-volatile storage elements in the group are programmed to a threshold voltage range based on the data states to which the plurality of pages have been mapped. The programming may include programming the “n” pages simultaneously. In one embodiment, mapping the plurality of pages is based on a coding scheme that distributes a significant failure mode (for example, program disturb errors) to a first of the pages and a significant failure mode (for example, data retention errors) to a second of the pages.

摘要翻译： 本文描述了用于操作非易失性存储器的非易失性存储设备和技术。 一个实施例包括访问要编程到一组非易失性存储元件中的“n”页数据。 基于在“n”页数据上均匀分布读取错误的编码方案，将“n”个页映射到每个非易失性存储元件的数据状态。 基于已经映射了多个页面的数据状态，组中的每个非易失性存储元件被编程到阈值电压范围。 编程可以包括同时对“n”页进行编程。 在一个实施例中，映射多个页面是基于将显着的故障模式（例如，程序干扰错误）分配给第一页面的编码方案和将重大故障模式（例如，数据保留错误）分配给 第二页。

公开(公告)号：US07652918B2

公开(公告)日：2010-01-26

申请号：US11617546

申请日：2006-12-28

申请人： Jun Wan ,  Jeffrey W. Lutze ,  Jian Chen ,  Yan Li ,  Alex Mak

发明人： Jun Wan ,  Jeffrey W. Lutze ,  Jian Chen ,  Yan Li ,  Alex Mak

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C16/3459 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3454 ,  G11C2211/5621

摘要： A memory system, comprising an array of storage elements divided into logical blocks and pages within said logical blocks and a managing circuit is provided. The managing circuit is in communication with said array of storage elements and performs programming and reading operations. The programming operations include programming a plurality of multi-state storage data. The reading operations include defining an retention margin between adjacent data thresholds, determining whether bits are present in a portion of the data retention margin, and if the number of bits in the portion of retention margin exceeds a threshold, generating an error.

摘要翻译： 一种存储器系统，包括分成逻辑块的存储元件阵列和所述逻辑块内的页面，并且提供管理电路。 管理电路与所述存储元件阵列通信并执行编程和读取操作。 编程操作包括编程多个多状态存储数据。 读取操作包括定义相邻数据阈值之间的保留余量，确定位是否存在于数据保留余量的一部分中，以及如果保留余量部分中的位数超过阈值，则产生错误。

公开(公告)号：US07414894B2

公开(公告)日：2008-08-19

申请号：US11389557

申请日：2006-03-23

申请人： Jeffrey W. Lutze ,  Jian Chen ,  Yan Li ,  Kazunori Kanebako ,  Tomoharu Tanaka

发明人： Jeffrey W. Lutze ,  Jian Chen ,  Yan Li ,  Kazunori Kanebako ,  Tomoharu Tanaka

IPC分类号： G11C11/34

CPC分类号： G11C16/3495 ,  G11C16/04 ,  G11C16/349 ,  G11C29/50 ,  G11C29/50004

摘要： A number of methods for identifying cells with poor subthreshold slope and reduced transconductance. A first set of techniques focuses on the poor subthreshold behavior of degraded storage elements by cycling cells and then programming them to a state above the ground state and the reading them with a control gate voltage below the threshold voltage of this state to see if they still conduct. A second set of embodiments focuses on weak transconductance behavior by reading programmed cells with a control gate voltage well above the threshold voltage. A third set of embodiments alters the voltage levels at the source-drain regions of the storage elements. The current-voltage curve of a good storage element is relatively stable under this shift in bias conditions, while degraded elements exhibit a larger shift. The amount of shift can be used to differentiate the good elements from the bad.

摘要翻译： 用于鉴定具有差的亚阈值斜率和降低的跨导的细胞的许多方法。 第一组技术集中在通过循环单元对劣化的存储元件的差的亚阈值行为进行编程，然后将它们编程到高于基态的状态，并以低于该状态的阈值电压的控制栅极电压读取它们，以查看它们是否仍然 进行。 第二组实施例通过利用远高于阈值电压的控制栅极电压读取编程单元来侧重于弱跨导行为。 第三组实施例改变存储元件的源极 - 漏极区域处的电压电平。 在偏置条件下的这种偏移下，良好存储元件的电流 - 电压曲线相对稳定，而退化元件表现出较大的偏移。 偏移量可以用来区分好的元素和坏的元素。

公开(公告)号：US07414886B2

公开(公告)日：2008-08-19

申请号：US11616778

申请日：2006-12-27

申请人： Yan Li ,  Jian Chen

发明人： Yan Li ,  Jian Chen

IPC分类号： G11C16/26

CPC分类号： G11C16/26 ,  G11C11/5642 ,  G11C16/3418 ,  G11C16/3422

摘要： Shifts in the apparent charge stored on a floating gate (or other charge storing element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates (or other adjacent charge storing elements). The problem occurs most pronouncedly between sets of adjacent memory cells that have been programmed at different times. To compensate for this coupling, the read process for a given memory cell will take into account the programmed state of an adjacent memory cell.

公开(公告)号：US20080158990A1

公开(公告)日：2008-07-03

申请号：US11617546

申请日：2006-12-28

申请人： Jun Wan ,  Jeffrey W. Lutze ,  Jian Chen ,  Yan Li ,  Alex Mak

发明人： Jun Wan ,  Jeffrey W. Lutze ,  Jian Chen ,  Yan Li ,  Alex Mak

IPC分类号： G11C16/34

CPC分类号： G11C16/3459 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3454 ,  G11C2211/5621

摘要： A memory system, comprising an array of storage elements divided into logical blocks and pages within said logical blocks and a managing circuit is provided. The managing circuit is in communication with said array of storage elements and performs programming and reading operations. The programming operations include programming a plurality of multi-state storage data. The reading operations include defining an retention margin between adjacent data thresholds, determining whether bits are present in a portion of the data retention margin, and if the number of bits in the portion of retention margin exceeds a threshold, generating an error.

摘要翻译： 一种存储器系统，包括分成逻辑块的存储元件阵列和所述逻辑块内的页面，并且提供管理电路。 管理电路与所述存储元件阵列通信并执行编程和读取操作。 编程操作包括编程多个多状态存储数据。 读取操作包括定义相邻数据阈值之间的保留余量，确定位是否存在于数据保留余量的一部分中，以及如果保留余量部分中的位数超过阈值，则产生错误。

公开(公告)号：US20080158989A1

公开(公告)日：2008-07-03

申请号：US11617541

申请日：2006-12-28

申请人： Jun Wan ,  Jeffrey W. Lutze ,  Jian Chen ,  Yan Li ,  Alex Mak

发明人： Jun Wan ,  Jeffrey W. Lutze ,  Jian Chen ,  Yan Li ,  Alex Mak

IPC分类号： G11C16/34

CPC分类号： G11C16/0483 ,  G11C11/5628 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2211/5621

摘要： Data verification in a memory device using a portion of a data retention margin is provided. A bit count is read from the region to determine whether errors will result in the memory. A read in one or more retention margin portions is performed after the normal program verify sequence and if the number of bits in these regions is more than a pre-set the memory will fail verify status. A method of verifying data in a memory device includes the steps of: defining an retention margin between adjacent data thresholds; programming the memory device with data; determining whether bits are present in the data retention margin; and if the number of bits in the retention margin exceeds a threshold, generating an error.

摘要翻译： 提供了使用部分数据保留余量的存储器件中的数据验证。 从区域读取位计数，以确定错误是否会导致内存。 在正常程序验证序列之后执行在一个或多个保留边缘部分中的读取，并且如果这些区域中的位数大于预设，则存储器将失败验证状态。 验证存储器件中的数据的方法包括以下步骤：定义相邻数据阈值之间的保留余量; 使用数据对存储设备进行编程; 确定位是否存在于数据保留余量中; 并且如果保留余量中的比特数超过阈值，则产生错误。

公开(公告)号：US20080043526A1

公开(公告)日：2008-02-21

申请号：US11923126

申请日：2007-10-24

申请人： Yan Li ,  Jian Chen ,  Raul-Adrian Cernea

发明人： Yan Li ,  Jian Chen ,  Raul-Adrian Cernea

IPC分类号： G11C16/04

CPC分类号： G11C16/3427 ,  G11C16/0483 ,  G11C16/12 ,  G11C16/28 ,  G11C16/3418

摘要： The present invention presents a non-volatile memory having a plurality of erase units or blocks, where each block is divided into a plurality of parts sharing the same word lines to save on the row decoder area, but which can be read or programmed independently. An exemplary embodiment is a Flash EEPROM memory with a NAND architecture that has blocks composed of a left half and a right half, where each part will accommodate one or more standard page (data transfer unit) sizes of 512 bytes of data. In the exemplary embodiment, the left and right portions of a block each have separate source lines, and separate sets of source and drain select lines. During the programming or reading of the left side, as an example, the right side can be biased to produce channel boosting to reduce data disturbs. In an alternate set of embodiments, the parts can have separate well structures.

摘要翻译： 本发明提供了一种具有多个擦除单元或块的非易失性存储器，其中每个块被分成多个部分，共享相同的字线以保存在行解码器区域上，但可独立地读取或编程。 一个示例性实施例是具有NAND架构的闪存EEPROM存储器，其具有由左半部分和右半部分组成的块，其中每个部分将容纳512字节数据的一个或多个标准页面（数据传送单元）大小。 在示例性实施例中，块的左侧和右侧部分各自具有分离的源极线，以及分离的源极和漏极选择线组。 在左侧的编程或读取期间，作为示例，右侧可以被偏置以产生信道增强以减少数据干扰。 在另一组实施例中，这些部件可以具有单独的井结构。

公开(公告)号：US07301839B2

公开(公告)日：2007-11-27

申请号：US11616769

申请日：2006-12-27

申请人： Yan Li ,  Jian Chen

发明人： Yan Li ,  Jian Chen

IPC分类号： G11C7/00

CPC分类号： G11C16/26 ,  G11C11/5642 ,  G11C16/3418 ,  G11C16/3422

摘要： Shifts in the apparent charge stored on a floating gate (or other charge storing element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates (or other adjacent charge storing elements). The problem occurs most pronouncedly between sets of adjacent memory cells that have been programmed at different times. To compensate for this coupling, the read process for a given memory cell will take into account the programmed state of an adjacent memory cell.

公开(公告)号：US07301808B2

公开(公告)日：2007-11-27

申请号：US11616757

申请日：2006-12-27

申请人： Yan Li ,  Jian Chen

发明人： Yan Li ,  Jian Chen

IPC分类号： G11C11/34

CPC分类号： G11C16/26 ,  G11C11/5642 ,  G11C16/3418 ,  G11C16/3422

摘要： Shifts in the apparent charge stored on a floating gate (or other charge storing element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates (or other adjacent charge storing elements). The problem occurs most pronouncedly between sets of adjacent memory cells that have been programmed at different times. To compensate for this coupling, the read process for a given memory cell will take into account the programmed state of an adjacent memory cell.