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    INCREASING BODY DOPANT UNIFORMITY IN MULTI-GATE TRANSISTOR DEVICES
    33.
    发明申请
    INCREASING BODY DOPANT UNIFORMITY IN MULTI-GATE TRANSISTOR DEVICES 有权
    在多栅极晶体管器件中增加身体钆的均匀性

    公开(公告)号：US20090267161A1

    公开(公告)日：2009-10-29

    申请号：US12111714

    申请日：2008-04-29

    申请人： Ravi Pillarisetty ,  Jack T. Kavalieros ,  Titash Rakshit ,  Gilbert Dewey ,  Willy Rachmady

    发明人： Ravi Pillarisetty ,  Jack T. Kavalieros ,  Titash Rakshit ,  Gilbert Dewey ,  Willy Rachmady

    IPC分类号： H01L29/76 ,  H01L21/336

    CPC分类号： H01L29/66545 ,  H01L29/66795

    摘要： Techniques and structures for increasing body dopant uniformity in multi-gate transistor devices are generally described. In one example, an electronic device includes a semiconductor substrate, a multi-gate fin coupled with the semiconductor substrate, the multi-gate fin comprising a source region, a drain region, and a gate region wherein the gate region is disposed between the source region and the drain region, the gate region being body-doped after a sacrificial gate structure is removed from the multi-gate fin and before a subsequent gate structure is formed, a dielectric material coupled with the source region and the drain region of the multi-gate fin, and the subsequent gate structure coupled to the gate region of the multi-gate fin.

    摘要翻译： 通常描述用于增加多栅极晶体管器件中的体掺杂物均匀性的技术和结构。 在一个示例中，电子设备包括半导体衬底，与半导体衬底耦合的多栅极鳍片，多栅极鳍片，包括源极区域，漏极区域和栅极区域，其中栅极区域设置在源极 区域和漏极区域，在从多栅极鳍去除牺牲栅极结构之后并且在形成后续栅极结构之后，栅极区域被体掺杂，与多层栅极的源极区域和漏极区域耦合的介电材料 并且随后的栅极结构耦合到多栅极鳍的栅极区域。

    Increasing body dopant uniformity in multi-gate transistor devices
    36.
    发明授权
    Increasing body dopant uniformity in multi-gate transistor devices 有权
    增加多栅极晶体管器件中的体掺杂均匀性

    公开(公告)号：US08022487B2

    公开(公告)日：2011-09-20

    申请号：US12111714

    申请日：2008-04-29

    申请人： Ravi Pillarisetty ,  Jack T. Kavalieros ,  Titash Rakshit ,  Gilbert Dewey ,  Willy Rachmady

    发明人： Ravi Pillarisetty ,  Jack T. Kavalieros ,  Titash Rakshit ,  Gilbert Dewey ,  Willy Rachmady

    IPC分类号： H01L21/00

    CPC分类号： H01L29/66545 ,  H01L29/66795

    摘要： Techniques and structures for increasing body dopant uniformity in multi-gate transistor devices are generally described. In one example, an electronic device includes a semiconductor substrate, a multi-gate fin coupled with the semiconductor substrate, the multi-gate fin comprising a source region, a drain region, and a gate region wherein the gate region is disposed between the source region and the drain region, the gate region being body-doped after a sacrificial gate structure is removed from the multi-gate fin and before a subsequent gate structure is formed, a dielectric material coupled with the source region and the drain region of the multi-gate fin, and the subsequent gate structure coupled to the gate region of the multi-gate fin.

    摘要翻译： 通常描述用于增加多栅极晶体管器件中的体掺杂物均匀性的技术和结构。 在一个示例中，电子设备包括半导体衬底，与半导体衬底耦合的多栅极鳍片，多栅极鳍片，包括源极区域，漏极区域和栅极区域，其中栅极区域设置在源极 区域和漏极区域，在从多栅极鳍去除牺牲栅极结构之后并且在形成后续栅极结构之后，栅极区域被体掺杂，与多层栅极的源极区域和漏极区域耦合的介电材料 并且随后的栅极结构耦合到多栅极鳍的栅极区域。

    Trigate transistor having extended metal gate electrode
    39.
    发明申请
    Trigate transistor having extended metal gate electrode 有权
    用具有扩展金属栅电极的晶体管

    公开(公告)号：US20100163970A1

    公开(公告)日：2010-07-01

    申请号：US12317966

    申请日：2008-12-31

    申请人： Titash Rakshit ,  Stephen M. Cea ,  Jack T. Kavalieros ,  Ravi Pillarisetty

    发明人： Titash Rakshit ,  Stephen M. Cea ,  Jack T. Kavalieros ,  Ravi Pillarisetty

    IPC分类号： H01L29/78

    CPC分类号： H01L29/785 ,  H01L29/66795

    摘要： A trigate device having an extended metal gate electrode comprises a semiconductor body having a top surface and opposing sidewalls formed on a substrate, an isolation layer formed on the substrate and around the semiconductor body, wherein a portion of the semiconductor body remains exposed above the isolation layer, and a gate stack formed on the top surface and opposing sidewalls of the semiconductor body, wherein the gate stack extends a depth into the isolation layer, thereby causing a bottom surface of the gate stack to be below a top surface of the isolation layer.

    摘要翻译： 具有延伸的金属栅电极的触发装置包括半导体本体，其具有形成在基板上的顶表面和相对的侧壁，形成在基板上并围绕半导体主体的隔离层，其中半导体主体的一部分保持暴露在隔离物的上方 层，以及形成在半导体主体的顶表面和相对侧壁上的栅极堆叠，其中栅极堆叠将深度延伸到隔离层中，从而使栅极堆叠的底表面在隔离层的顶表面下方 。