公开(公告)号：US08188574B2

公开(公告)日：2012-05-29

申请号：US12704567

申请日：2010-02-12

申请人： Matthew S. Angyal ,  Mahender Kumar ,  Effendi Leobandung ,  Jay W. Strane

发明人： Matthew S. Angyal ,  Mahender Kumar ,  Effendi Leobandung ,  Jay W. Strane

IPC分类号： H01L29/72

CPC分类号： H01L23/585 ,  H01L21/76264 ,  H01L23/562 ,  H01L2924/0002 ,  H01L2924/00

摘要： A microelectronic element, e.g., a semiconductor chip having a silicon-on-insulator layer (“SOI layer”) separated from a bulk monocrystalline silicon layer by a buried oxide (BOX) layer in which a crack stop extends in first lateral directions at least generally parallel to the edges of the chip to define a ring-like barrier separating an active portion of the chip inside the barrier with a peripheral portion of the chip. The crack stop can include a first crack stop ring contacting a silicon portion of the chip above the BOX layer; the first crack stop ring may extend continuously in the first lateral directions to surround the active portion of the chip. A guard ring (“GR”) including a GR contact ring can extend downwardly through the SOI layer and the BOX layer to conductively contact the bulk monocrystalline silicon region, the GR contact ring extending at least generally parallel to the first crack stop ring to surround the active portion of the chip. A continuous metal ring extending continuously in the first lateral directions can surround the active portion of the chip, such metal ring connecting the GR contact ring with the first crack stop ring such that the metal line and the GR contact ring form a continuous seal preventing mobile ions from moving between the peripheral and active portions of the chip.

摘要翻译： 微电子元件，例如具有通过掩埋氧化物（BOX）层与大块单晶硅层分离的绝缘体上硅层（“SOI层”）的半导体芯片，其中裂纹阻挡层在第一横向至少延伸至少 通常平行于芯片的边缘以限定将芯片内的芯片的有源部分与芯片的周边部分分开的环状势垒。 裂纹停止件可以包括与BOX层上方的芯片的硅部分接触的第一裂纹阻挡环; 第一裂纹阻挡环可以在第一横向方向上连续延伸以围绕芯片的有效部分。 包括GR接触环的保护环（“GR”）可以向下延伸穿过SOI层和BOX层以导电接触大块单晶硅区域，GR接触环至少大致平行于第一裂纹阻挡环延伸以包围 芯片的有效部分。 在第一横向方向上连续延伸的连续金属环可以围绕芯片的有效部分，这种金属环将GR接触环与第一裂纹阻止环连接，使得金属线和GR接触环形成连续的密封，防止移动 离子在芯片的外围和有源部分之间移动。

公开(公告)号：US07911024B2

公开(公告)日：2011-03-22

申请号：US12707305

申请日：2010-02-17

申请人： Herbert L. Ho ,  Mahender Kumar ,  Qiqing Ouyang ,  Paul A. Papworth ,  Christopher D. Sheraw ,  Michael D. Steigerwalt

发明人： Herbert L. Ho ,  Mahender Kumar ,  Qiqing Ouyang ,  Paul A. Papworth ,  Christopher D. Sheraw ,  Michael D. Steigerwalt

IPC分类号： H01L27/102

CPC分类号： H01L29/7317

摘要： The present invention provides a “collector-less” silicon-on-insulator (SOI) bipolar junction transistor (BJT) that has no impurity-doped collector. Instead, the inventive vertical SOI BJT uses a back gate-induced, minority carrier inversion layer as the intrinsic collector when it operates. In accordance with the present invention, the SOI substrate is biased such that an inversion layer is formed at the bottom of the base region serving as the collector. The advantage of such a device is its CMOS-like process. Therefore, the integration scheme can be simplified and the manufacturing cost can be significantly reduced. The present invention also provides a method of fabricating BJTs on selected areas of a very thin BOX using a conventional SOI starting wafer with a thick BOX. The reduced BOX thickness underneath the bipolar devices allows for a significantly reduced substrate bias compatible with the CMOS to be applied while maintaining the advantages of a thick BOX underneath the CMOS.

摘要翻译： 本发明提供一种没有杂质掺杂的集电极的“无集电极”绝缘体上硅（SOI）双极结型晶体管（BJT）。 相反，本发明的垂直SOI BJT在其操作时使用背栅诱发的少数载流子反转层作为固有收集器。 根据本发明，SOI衬底被偏置，使得在用作集电极的基极区域的底部形成反型层。 这种器件的优点是其类似CMOS的工艺。 因此，可以简化集成方案，并且可以显着降低制造成本。 本发明还提供了使用具有厚BOX的常规SOI起始晶片在非常薄的BOX的选定区域上制造BJT的方法。 双极器件下面的BOX厚度减小，可以显着降低与CMOS相容的衬底偏置，同时保持CMOS下方的厚BOX的优点。

公开(公告)号：US20100207683A1

公开(公告)日：2010-08-19

申请号：US12707305

申请日：2010-02-17

申请人： Herbert L. Ho ,  Mahender Kumar ,  Qiqing Ouyang ,  Paul A. Papworth ,  Christopher D. Sheraw ,  Michael D. Steigerwalt

发明人： Herbert L. Ho ,  Mahender Kumar ,  Qiqing Ouyang ,  Paul A. Papworth ,  Christopher D. Sheraw ,  Michael D. Steigerwalt

IPC分类号： H03K3/01 ,  H01L29/73

CPC分类号： H01L29/7317

摘要： The present invention provides a “collector-less” silicon-on-insulator (SOI) bipolar junction transistor (BJT) that has no impurity-doped collector. Instead, the inventive vertical SOI BJT uses a back gate-induced, minority carrier inversion layer as the intrinsic collector when it operates. In accordance with the present invention, the SOI substrate is biased such that an inversion layer is formed at the bottom of the base region serving as the collector. The advantage of such a device is its CMOS-like process. Therefore, the integration scheme can be simplified and the manufacturing cost can be significantly reduced. The present invention also provides a method of fabricating BJTs on selected areas of a very thin BOX using a conventional SOI starting wafer with a thick BOX. The reduced BOX thickness underneath the bipolar devices allows for a significantly reduced substrate bias compatible with the CMOS to be applied while maintaining the advantages of a thick BOX underneath the CMOS.

摘要翻译： 本发明提供一种没有杂质掺杂的集电极的“无集电极”绝缘体上硅（SOI）双极结型晶体管（BJT）。 相反，本发明的垂直SOI BJT在其操作时使用背栅诱发的少数载流子反转层作为固有收集器。 根据本发明，SOI衬底被偏置，使得在用作集电极的基极区域的底部形成反型层。 这种器件的优点是其类似CMOS的工艺。 因此，可以简化集成方案，并且可以显着降低制造成本。 本发明还提供了使用具有厚BOX的常规SOI起始晶片在非常薄的BOX的选定区域上制造BJT的方法。 双极器件下面的BOX厚度减小，可以显着降低与CMOS相容的衬底偏置，同时保持CMOS下方的厚BOX的优点。

公开(公告)号：US20100200958A1

公开(公告)日：2010-08-12

申请号：US12704567

申请日：2010-02-12

申请人： Matthew S. Angyal ,  Mahender Kumar ,  Effendi Leobandung ,  Jay W. Strane

发明人： Matthew S. Angyal ,  Mahender Kumar ,  Effendi Leobandung ,  Jay W. Strane

IPC分类号： H01L23/00 ,  H01L21/762

CPC分类号： H01L23/585 ,  H01L21/76264 ,  H01L23/562 ,  H01L2924/0002 ,  H01L2924/00

摘要： A microelectronic element, e.g., a semiconductor chip having a silicon-on-insulator layer (“SOI layer”) separated from a bulk monocrystalline silicon layer by a buried oxide (BOX) layer in which a crack stop extends in first lateral directions at least generally parallel to the edges of the chip to define a ring-like barrier separating an active portion of the chip inside the barrier with a peripheral portion of the chip. The crack stop can include a first crack stop ring contacting a silicon portion of the chip above the BOX layer; the first crack stop ring may extend continuously in the first lateral directions to surround the active portion of the chip. A guard ring (“GR”) including a GR contact ring can extend downwardly through the SOI layer and the BOX layer to conductively contact the bulk monocrystalline silicon region, the GR contact ring extending at least generally parallel to the first crack stop ring to surround the active portion of the chip. A continuous metal ring extending continuously in the first lateral directions can surround the active portion of the chip, such metal ring connecting the GR contact ring with the first crack stop ring such that the metal line and the GR contact ring form a continuous seal preventing mobile ions from moving between the peripheral and active portions of the chip.

摘要翻译： 微电子元件，例如具有通过掩埋氧化物（BOX）层与大块单晶硅层分离的绝缘体上硅层（“SOI层”）的半导体芯片，其中裂纹阻挡层在第一横向至少延伸至少 通常平行于芯片的边缘以限定将芯片内的芯片的有源部分与芯片的周边部分分开的环状势垒。 裂纹停止件可以包括与BOX层上方的芯片的硅部分接触的第一裂纹阻挡环; 第一裂纹阻挡环可以在第一横向方向上连续延伸以围绕芯片的有效部分。 包括GR接触环的保护环（“GR”）可以向下延伸穿过SOI层和BOX层以导电接触大块单晶硅区域，GR接触环至少大致平行于第一裂纹阻挡环延伸以包围 芯片的有效部分。 在第一横向方向上连续延伸的连续金属环可以围绕芯片的有效部分，这种金属环将GR接触环与第一裂纹阻止环连接，使得金属线和GR接触环形成连续的密封，防止移动 离子在芯片的外围和有源部分之间移动。

公开(公告)号：US07691716B2

公开(公告)日：2010-04-06

申请号：US12144998

申请日：2008-06-24

申请人： Herbert L. Ho ,  Mahender Kumar ,  Qiging Ouyang ,  Paul A. Papworth ,  Christopher D. Sheraw ,  Michael D. Steigerwalt

发明人： Herbert L. Ho ,  Mahender Kumar ,  Qiging Ouyang ,  Paul A. Papworth ,  Christopher D. Sheraw ,  Michael D. Steigerwalt

IPC分类号： H01L21/331 ,  H01L21/8222

CPC分类号： H01L29/7317 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0821 ,  H01L29/66265

摘要： The present invention provides a “subcollector-less” silicon-on-insulator (SOI) bipolar junction transistor (BJT) that has no impurity-doped subcollector. Instead, the inventive vertical SOI BJT uses a back gate-induced, majority carrier accumulation layer as the subcollector when it operates. The SOI substrate is biased such that the accumulation layer is formed at the bottom of the first semiconductor layer. The advantage of such a device is its CMOS-like process. Therefore, the integration scheme can be simplified and the manufacturing cost can be significantly reduced. The present invention also provides a method of fabricating BJTs on selected areas of a very thin BOX using a conventional SOI starting wafer with a thick BOX. The reduced BOX thickness underneath the bipolar devices allows for a significantly reduced substrate bias compatible with the CMOS to be applied while maintaining the advantages of a thick BOX underneath the CMOS. A back-gated CMOS device is also provided.

摘要翻译： 本发明提供了一种不含杂质掺杂子集电极的“不带集电极的绝缘体上硅”（SOI）双极结型晶体管（BJT）。 相反，本发明的垂直SOI BJT在操作时使用背栅极多数载流子积累层作为子集电极。 SOI衬底被偏置，使得积累层形成在第一半导体层的底部。 这种器件的优点是其类似CMOS的工艺。 因此，可以简化集成方案，并且可以显着降低制造成本。 本发明还提供了使用具有厚BOX的常规SOI起始晶片在非常薄的BOX的选定区域上制造BJT的方法。 双极器件下面的BOX厚度减小，可以显着降低与CMOS相容的衬底偏置，同时保持CMOS下方的厚BOX的优点。 还提供了背栅CMOS装置。

公开(公告)号：US20100006926A1

公开(公告)日：2010-01-14

申请号：US12170687

申请日：2008-07-10

申请人： HUILONG ZHU ,  Xiaomeng Chen ,  Mahender Kumar ,  Brian J. Greene ,  Bachir Dirahoui ,  Jay W. Strane ,  Gregory G. Freeman

发明人： HUILONG ZHU ,  Xiaomeng Chen ,  Mahender Kumar ,  Brian J. Greene ,  Bachir Dirahoui ,  Jay W. Strane ,  Gregory G. Freeman

IPC分类号： H01L27/088 ,  H01L21/8234

CPC分类号： H01L21/823842 ,  H01L21/82385 ,  H01L21/823857

摘要： Methods for forming high performance gates in MOSFETs and structures thereof are disclosed. One embodiment includes a method including providing a substrate including a first short channel active region, a second short channel active region and a long channel active region, each active region separated from another by a shallow trench isolation (STI); and forming a field effect transistor (FET) with a polysilicon gate over the long channel active region, a first dual metal gate FET having a first work function adjusting material over the first short channel active region and a second dual metal gate FET having a second work function adjusting material over the second short channel active region, wherein the first and second work function adjusting materials are different.

摘要翻译： 公开了在MOSFET中形成高性能栅极的方法及其结构。 一个实施例包括提供包括第一短沟道有源区，第二短沟道有源区和长沟道有源区的衬底的方法，每个有源区通过浅沟槽隔离（STI）与另一个分离。 以及在所述长沟道有源区上形成具有多晶硅栅极的场效应晶体管（FET），在所述第一短沟道有源区上具有第一功函数调节材料的第一双金属栅极FET和具有第二双金属栅极FET的第二双金属栅极FET， 第二短通道有源区域上的功函数调整材料，其中第一和第二功函数调节材料不同。

公开(公告)号：US20090256207A1

公开(公告)日：2009-10-15

申请号：US12102333

申请日：2008-04-14

申请人： Xiaomeng Chen ,  Bachir Dirahoui ,  William K. Henson ,  Michael D. Hulvey ,  Amit Kumar ,  Mahender Kumar ,  Amanda L. Tessier ,  Clement H. Wann

发明人： Xiaomeng Chen ,  Bachir Dirahoui ,  William K. Henson ,  Michael D. Hulvey ,  Amit Kumar ,  Mahender Kumar ,  Amanda L. Tessier ,  Clement H. Wann

IPC分类号： H01L27/088 ,  H01L21/336

CPC分类号： H01L29/785 ,  H01L21/76283 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/66795

摘要： Disclosed herein is a transistor comprising a first fin having a first gate electrode disposed across the first fin; the gate electrode contacting opposing surfaces of the fin; and a planar oxide layer having a second gate electrode disposed across the planar oxide layer to form a planar metal oxide semiconductor field effect transistor; the first fin and the planar oxide layer being disposed upon a surface of a wafer.

摘要翻译： 本文公开了一种晶体管，包括：第一鳍片，其具有横跨第一鳍片设置的第一栅电极; 所述栅电极接触所述翅片的相对表面; 以及平面氧化物层，具有跨过所述平面氧化物层设置的第二栅极，以形成平面金属氧化物半导体场效应晶体管; 第一鳍片和平面氧化物层设置在晶片的表面上。

公开(公告)号：US20080230869A1

公开(公告)日：2008-09-25

申请号：US12099437

申请日：2008-04-08

申请人： Herbert L. Ho ,  Mahender Kumar ,  Qiqing Ouyang ,  Paul A. Papworth ,  Christopher D. Sheraw ,  Michael D. Steigerwalt

发明人： Herbert L. Ho ,  Mahender Kumar ,  Qiqing Ouyang ,  Paul A. Papworth ,  Christopher D. Sheraw ,  Michael D. Steigerwalt

IPC分类号： H01L29/732 ,  H01L21/331

CPC分类号： H01L29/7317

摘要： The present invention provides a “collector-less” silicon-on-insulator (SOI) bipolar junction transistor (BJT) that has no impurity-doped collector. Instead, the inventive vertical SOI BJT uses a back gate-induced, minority carrier inversion layer as the intrinsic collector when it operates. In accordance with the present invention, the SOI substrate is biased such that an inversion layer is formed at the bottom of the base region serving as the collector. The advantage of such a device is its CMOS-like process. Therefore, the integration scheme can be simplified and the manufacturing cost can be significantly reduced. The present invention also provides a method of fabricating BJTs on selected areas of a very thin BOX using a conventional SOI starting wafer with a thick BOX. The reduced BOX thickness underneath the bipolar devices allows for a significantly reduced substrate bias compatible with the CMOS to be applied while maintaining the advantages of a thick BOX underneath the CMOS.

摘要翻译： 本发明提供一种没有杂质掺杂的集电极的“无集电极”绝缘体上硅（SOI）双极结型晶体管（BJT）。 相反，本发明的垂直SOI BJT在其操作时使用背栅诱发的少数载流子反转层作为固有收集器。 根据本发明，SOI衬底被偏置，使得在用作集电极的基极区域的底部形成反型层。 这种器件的优点是其类似CMOS的工艺。 因此，可以简化集成方案，并且可以显着降低制造成本。 本发明还提供了使用具有厚BOX的常规SOI起始晶片在非常薄的BOX的选定区域上制造BJT的方法。 双极器件下面的BOX厚度减小，可以显着降低与CMOS相容的衬底偏置，同时保持CMOS下方的厚BOX的优点。

公开(公告)号：US07375410B2

公开(公告)日：2008-05-20

申请号：US10787002

申请日：2004-02-25

申请人： Herbert L. Ho ,  Mahender Kumar ,  Qiqing Ouyang ,  Paul A. Papworth ,  Christopher D. Sheraw ,  Michael D. Steigerwalt

发明人： Herbert L. Ho ,  Mahender Kumar ,  Qiqing Ouyang ,  Paul A. Papworth ,  Christopher D. Sheraw ,  Michael D. Steigerwalt

IPC分类号： H01L27/102

CPC分类号： H01L29/7317

摘要： The present invention provides a “collector-less” silicon-on-insulator (SOI) bipolar junction transistor (BJT) that has no impurity-doped collector. Instead, the inventive vertical SOI BJT uses a back gate-induced, minority carrier inversion layer as the intrinsic collector when it operates. In accordance with the present invention, the SOI substrate is biased such that an inversion layer is formed at the bottom of the base region serving as the collector. The advantage of such a device is its CMOS-like process. Therefore, the integration scheme can be simplified and the manufacturing cost can be significantly reduced. The present invention also provides a method of fabricating BJTs on selected areas of a very thin BOX using a conventional SOI starting wafer with a thick BOX. The reduced BOX thickness underneath the bipolar devices allows for a significantly reduced substrate bias compatible with the CMOS to be applied while maintaining the advantages of a thick BOX underneath the CMOS.

摘要翻译： 本发明提供一种没有杂质掺杂的集电极的“无集电极”绝缘体上硅（SOI）双极结型晶体管（BJT）。 相反，本发明的垂直SOI BJT在其操作时使用背栅诱发的少数载流子反转层作为固有收集器。 根据本发明，SOI衬底被偏置，使得在用作集电极的基极区域的底部形成反型层。 这种器件的优点是其类似CMOS的工艺。 因此，可以简化集成方案，并且可以显着降低制造成本。 本发明还提供了使用具有厚BOX的常规SOI起始晶片在非常薄的BOX的选定区域上制造BJT的方法。 双极器件下面的BOX厚度减小，可以显着降低与CMOS相容的衬底偏置，同时保持CMOS下方的厚BOX的优点。

公开(公告)号：US20060043530A1

公开(公告)日：2006-03-02

申请号：US10931855

申请日：2004-09-01

申请人： Herbert Ho ,  Mahender Kumar ,  Qiqing Ouyang ,  Paul Papworth ,  Christopher Sheraw ,  Michael Steigerwalt

发明人： Herbert Ho ,  Mahender Kumar ,  Qiqing Ouyang ,  Paul Papworth ,  Christopher Sheraw ,  Michael Steigerwalt

IPC分类号： H01L27/01

CPC分类号： H01L29/7317 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0821 ,  H01L29/66265

摘要： The present invention provides a “subcollector-less” silicon-on-insulator (SOI) bipolar junction transistor (BJT) that has no impurity-doped subcollector. Instead, the inventive vertical SOI BJT uses a back gate-induced, majority carrier accumulation layer as the subcollector when it operates. The SOI substrate is biased such that the accumulation layer is formed at the bottom of the first semiconductor layer. The advantage of such a device is its CMOS-like process. Therefore, the integration scheme can be simplified and the manufacturing cost can be significantly reduced. The present invention also provides a method of fabricating BJTs on selected areas of a very thin BOX using a conventional SOI starting wafer with a thick BOX. The reduced BOX thickness underneath the bipolar devices allows for a significantly reduced substrate bias compatible with the CMOS to be applied while maintaining the advantages of a thick BOX underneath the CMOS. A back-gated CMOS device is also provided.