公开(公告)号：US10446560B2

公开(公告)日：2019-10-15

申请号：US15986064

申请日：2018-05-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungwoo Kim ,  Bong-Soo Kim ,  Youngbae Kim ,  Kijae Hur ,  Gwanhyeob Koh ,  Hyeongsun Hong ,  Yoosang Hwang

IPC: H01L27/00 ,  H01L27/108 ,  H01L27/24 ,  H01L27/22

Abstract: A semiconductor device including: a first memory section, a first peripheral circuit section, and a second peripheral circuit section on a substrate; a second memory section on the second peripheral circuit section; and a wiring section between the second peripheral circuit section and the second memory section, the first memory section includes a plurality of first memory cells, the first memory cells each including a cell transistor and a capacitor connected to the cell transistor, the second memory section includes a plurality of second memory cells, the second memory cells each including a variable resistance element and a select element in series, and the wiring section includes a plurality of line patterns, at least one of the line patterns and at least one of the capacitors at the same level from the substrate, the second memory cells are higher from the substrate than the at least one of the capacitors.

公开(公告)号：US10431276B2

公开(公告)日：2019-10-01

申请号：US16290102

申请日：2019-03-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Boyoung Seo ,  Yongkyu Lee ,  Gwanhyeob Koh ,  Choong Jae Lee

IPC: G11C11/00 ,  G11C17/02 ,  G11C11/16 ,  H01L43/10 ,  H01L43/08 ,  H01L27/22

Abstract: A semiconductor device includes a memory cell array, which further includes an array of first magnetic memory cells and an array of second magnetic memory cells. Each of the first magnetic memory cells includes a first magnetic tunnel junction structure having a reversible resistance state, and each of the second magnetic memory cells includes a second magnetic tunnel junction structure having a one-time programmable (OTP) resistance state.

公开(公告)号：US10395706B2

公开(公告)日：2019-08-27

申请号：US15984914

申请日：2018-05-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungwoo Kim ,  Bong-Soo Kim ,  Youngbae Kim ,  Kijae Hur ,  Gwanhyeob Koh ,  Hyeongsun Hong ,  Yoosang Hwang

IPC: H01L27/00 ,  G11C11/00 ,  H01L23/528 ,  H01L27/108 ,  H01L27/24 ,  H01L49/02 ,  H01L45/00

Abstract: A semiconductor device including: a first memory section, a first peripheral circuit section, and a second peripheral circuit section that are disposed next to each other on a substrate; and a second memory section laterally spaced apart from the first memory section, the second peripheral circuit section and the second memory section disposed next to each other on the substrate, wherein the first memory section includes a plurality of first memory cells, each of the first memory cells including a cell transistor and a capacitor connected to the cell transistor, and the second memory section includes a plurality of second memory cells, each of the second memory cells including a variable resistance element and a select element coupled in series to each other, wherein the second memory cells are higher from the substrate than each of the capacitors.

公开(公告)号：US10103323B2

公开(公告)日：2018-10-16

申请号：US15704963

申请日：2017-09-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong-Seok Chung ,  Yoonjong Song ,  Yongkyu Lee ,  Gwanhyeob Koh

IPC: H01L21/302 ,  H01L43/12 ,  H01L21/266 ,  H01L21/027 ,  H01L27/22

Abstract: The inventive concepts provide a method for forming a hard mask pattern. The method includes forming a hard mask layer on an etch target layer disposed on a substrate, forming a photoresist pattern having an opening exposing one region of the hard mask layer, performing an oxygen ion implantation process on the one region using the photoresist pattern as a mask to form an oxidized portion in the one region, and patterning the hard mask layer using the oxidized portion as an etch mask.

公开(公告)号：US10032981B2

公开(公告)日：2018-07-24

申请号：US15244344

申请日：2016-08-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Shinhee Han ,  Kiseok Suh ,  KyungTae Nam ,  Woojin Kim ,  Kwangil Shin ,  Minkyoung Joo ,  Gwanhyeob Koh

IPC: H01L21/00 ,  H01L43/12 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L27/22 ,  G11C11/16

Abstract: A method of fabricating a magnetic memory device includes forming an interlayered insulating layer on a substrate, forming a landing pad to pass through the interlayered insulating layer, forming a protection insulating layer on the interlayered insulating layer to cover a top surface of the landing pad, forming a bottom electrode to pass through the protection insulating layer and through the interlayered insulating layer, forming a magnetic tunnel junction layer on the protection insulating layer; and patterning the magnetic tunnel junction layer to form a magnetic tunnel junction pattern on the bottom electrode.