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    Semiconductor devices
    1.
    发明授权
    Semiconductor devices 有权

    公开(公告)号：US11271038B2

    公开(公告)日：2022-03-08

    申请号：US17027980

    申请日：2020-09-22

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Myoungsu Son ,  Seung Pil Ko ,  Jung Hyuk Lee ,  Shinhee Han ,  Gwan-Hyeob Koh ,  Yoonjong Song

    IPC: H01L27/22 ,  H01L43/02 ,  H01L43/12 ,  H01L43/08 ,  H01L23/522

    Abstract: A semiconductor device includes a gate structure on a substrate, source and drain contacts respectively on opposite sides of the gate structure and connected to the substrate, a magnetic tunnel junction connected to the drain contact, a first conductive line connected to the source contact, and a second conductive line connected to the first conductive line through a first via contact. The second conductive line is distal to the substrate in relation to the first conductive line. The first and second conductive lines extend in parallel along a first direction. The first and second conductive lines have widths in a second direction intersecting the first direction. The widths of the first and second conductive lines are the same. The first via contact is aligned with the source contact along a third direction perpendicular to a top surface of the substrate.

    Magnetic memory device
    2.
    发明授权
    Magnetic memory device 有权

    公开(公告)号：US12035540B2

    公开(公告)日：2024-07-09

    申请号：US17380081

    申请日：2021-07-20

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Boyoung Seo ,  Kangho Lee ,  Yoonjong Song ,  Junghyuk Lee

    IPC: H10B61/00 ,  H10B20/20

    CPC classification number: H10B61/22 ,  H10B20/20

    Abstract: A magnetic memory device includes a plurality of first bit lines and a plurality of second bit lines, a plurality of first source lines respectively corresponding to the plurality of first bit lines and a plurality of second source lines respectively corresponding to the plurality of second bit lines, a plurality of first memory cells connected between the plurality of first bit lines and the plurality of first source lines, respectively, in a first region, the plurality of first memory cells respectively including a first memory device and a first selection transistor, and a plurality of second memory cells connected between the plurality of second bit lines and the plurality of second source lines, respectively, in a second region, the plurality of second memory cells respectively including a second memory device and a second selection transistor.

    MAGNETIC MEMORY DEVICE
    3.
    发明申请
    MAGNETIC MEMORY DEVICE 有权

    公开(公告)号：US20220028928A1

    公开(公告)日：2022-01-27

    申请号：US17380081

    申请日：2021-07-20

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Boyoung Seo ,  Kangho Lee ,  Yoonjong Song ,  Junghyuk Lee

    IPC: H01L27/22 ,  H01L27/112

    Abstract: A magnetic memory device includes a plurality of first bit lines and a plurality of second bit lines, a plurality of first source lines respectively corresponding to the plurality of first bit lines and a plurality of second source lines respectively corresponding to the plurality of second bit lines, a plurality of first memory cells connected between the plurality of first bit lines and the plurality of first source lines, respectively, in a first region, the plurality of first memory cells respectively including a first memory device and a first selection transistor, and a plurality of second memory cells connected between the plurality of second bit lines and the plurality of second source lines, respectively, in a second region, the plurality of second memory cells respectively including a second memory device and a second selection transistor.

    Magnetic memory device and method for manufacturing the same
    4.
    发明授权
    Magnetic memory device and method for manufacturing the same 有权

    公开(公告)号：US10897006B2

    公开(公告)日：2021-01-19

    申请号：US16286718

    申请日：2019-02-27

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kilho Lee ,  Gwanhyeob Koh ,  Yongjae Kim ,  Yoonjong Song

    IPC: H01L27/22 ,  H01L43/02 ,  H01L43/12

    Abstract: A magnetic memory device including a substrate including a cell region and a peripheral circuit region; a first interlayer insulating layer covering the cell region and the peripheral circuit region of the substrate; interconnection lines in the first interlayer insulating layer; a peripheral conductive line and a peripheral conductive contact on the first interlayer insulating layer on the peripheral circuit region, the peripheral conductive contact being between the peripheral conductive line and a corresponding one of the interconnection lines; a bottom electrode contact on the first interlayer insulating layer on the cell region and connected to a corresponding one of the interconnection lines; and a data storage pattern on the bottom electrode contact, wherein the peripheral conductive line is at a height between a top surface of the bottom electrode contact and a bottom surface of the bottom electrode contact.

    Semiconductor devices
    5.
    发明授权
    Semiconductor devices 有权

    公开(公告)号：US10818727B2

    公开(公告)日：2020-10-27

    申请号：US16161370

    申请日：2018-10-16

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Myoungsu Son ,  Seung Pil Ko ,  Jung Hyuk Lee ,  Shinhee Han ,  Gwan-Hyeob Koh ,  Yoonjong Song

    IPC: H01L27/22 ,  H01L43/02 ,  H01L43/12 ,  H01L43/08 ,  H01L23/522

    Abstract: A semiconductor device includes a gate structure on a substrate, source and drain contacts respectively on opposite sides of the gate structure and connected to the substrate, a magnetic tunnel junction connected to the drain contact, a first conductive line connected to the source contact, and a second conductive line connected to the first conductive line through a first via contact. The second conductive line is distal to the substrate in relation to the first conductive line. The first and second conductive lines extend in parallel along a first direction. The first and second conductive lines have widths in a second direction intersecting the first direction. The widths of the first and second conductive lines are the same. The first via contact is aligned with the source contact along a third direction perpendicular to a top surface of the substrate.

    Magnetic memory devices
    6.
    发明授权
    Magnetic memory devices 有权

    公开(公告)号：US10693055B2

    公开(公告)日：2020-06-23

    申请号：US16202360

    申请日：2018-11-28

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kilho Lee ,  Gwanhyeob Koh ,  Yoonjong Song

    IPC: H01L43/02 ,  H01L43/12 ,  H01L43/10 ,  H01L27/22

    Abstract: Magnetic random access memory (MRAM) devices are provided. The MRAM devices may include a magnetic tunnel junction (MTJ) including a free layer and a pinned layer sequentially stacked in a vertical direction and a conductive layer adjacent to the free layer of the MTJ. The conductive layer may include a horizontal portion and first and second protruding portions that protrude away from the horizontal portion and are spaced apart from each other in a horizontal direction that is perpendicular to the vertical direction. A side of the free layer and a side of the horizontal portion may form a straight side.

    Memory device and programming method
    8.
    发明授权
    Memory device and programming method 审中-公开

    公开(公告)号：US10672447B2

    公开(公告)日：2020-06-02

    申请号：US16262366

    申请日：2019-01-30

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hyunsung Jung ,  Hyemin Shin ,  Yoonjong Song ,  Jung Hyuk Lee

    IPC: G11C16/10 ,  G11C11/16 ,  H01L27/22 ,  H01L43/02 ,  H01L43/10

    Abstract: Disclosed is a memory device. The memory device includes a memory cell array that includes a target cell, a row decoder that drive a word line, and a write driver and sense amplifier that are configured to drive a bit line and a source line. The row decoder is configured to drive the word line in a first program operation and a second program operation. Between a start of the first program operation and an end of the second program operation, the write driver and sense amplifier are configured to continuously drive a bit line connected to the target cell with a second driving voltage or drive a source line connected to the target cell with a third driving voltage.

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