公开(公告)号：US09818748B2

公开(公告)日：2017-11-14

申请号：US15440541

申请日：2017-02-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-Dae Suk ,  Kang-Ill Seo

IPC: H01L21/00 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/84 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L27/0924 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823864 ,  H01L21/845 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/78618 ,  H01L29/78681 ,  H01L29/78684 ,  H01L29/78696

Abstract: A semiconductor device is provided. A substrate includes a first region and a second region. A first wire pattern, extending in a first direction, is formed at a first height from the substrate of the first region. A second wire pattern, extending in a second direction, is formed at a second height from the substrate of the second region. The first height is different from the second height. A first gate electrode, surrounding the first wire pattern, extends in a third direction crossing the first direction. A second gate electrode, surrounding the second wire pattern, extends in a fourth direction crossing the second direction. A first gate insulation layer is formed along a circumference of the first wire pattern and a sidewall of the first gate electrode. A second gate insulation layer is formed along a circumference of the second wire pattern and a sidewall of the second gate electrode.

公开(公告)号：US09653462B2

公开(公告)日：2017-05-16

申请号：US14583252

申请日：2014-12-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-Dae Suk ,  Kang-Ill Seo

IPC: H01L21/336 ,  H01L27/088 ,  H01L29/66 ,  H01L21/225 ,  H01L29/78 ,  H01L29/08 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/417

CPC classification number: H01L27/0886 ,  H01L21/225 ,  H01L21/76805 ,  H01L21/823425 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/485 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7851

Abstract: A semiconductor device includes a fin type active pattern extended in a first direction and disposed on a substrate. A first gate electrode and a second gate electrode are disposed on the fin type active pattern. The first gate electrode and the second gate electrode are extended in a second direction crossing the first direction. A trench region is disposed in the fin type active pattern and between the first gate electrode and the second gate electrode. A source/drain region is disposed on a surface of the trench region. A source/drain contact is disposed on the source/drain region. The source/drain contact includes a first insulating layer disposed on the source/drain region and a metal oxide layer disposed on the first insulating layer.

公开(公告)号：US20160190128A1

公开(公告)日：2016-06-30

申请号：US14583252

申请日：2014-12-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-Dae Suk ,  Kang-III Seo

IPC: H01L27/088 ,  H01L21/225 ,  H01L21/306 ,  H01L29/417 ,  H01L29/78 ,  H01L29/08 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/66 ,  H01L21/308

CPC classification number: H01L27/0886 ,  H01L21/225 ,  H01L21/76805 ,  H01L21/823425 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/485 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7851

Abstract: A semiconductor device includes a fin type active pattern extended in a first direction and disposed on a substrate. A first gate electrode and a second gate electrode are disposed on the fin type active pattern. The first gate electrode and the second gate electrode are extended in a second direction crossing the first direction. A trench region is disposed in the fin type active pattern and between the first gate electrode and the second gate electrode. A source/drain region is disposed on a surface of the trench region. A source/drain contact is disposed on the source/drain region. The source/drain contact includes a first insulating layer disposed on the source/drain region and a metal oxide layer disposed on the first insulating layer.

Abstract translation: 半导体器件包括在第一方向上延伸并设置在衬底上的鳍式有源图案。 第一栅电极和第二栅电极设置在鳍型活性图案上。 第一栅电极和第二栅电极沿与第一方向交叉的第二方向延伸。 沟槽区域设置在翅片型有源图案中，并且位于第一栅极电极和第二栅极电极之间。 源极/漏极区域设置在沟槽区域的表面上。 源极/漏极触点设置在源极/漏极区域上。 源极/漏极接触包括设置在源极/漏极区域上的第一绝缘层和设置在第一绝缘层上的金属氧化物层。

公开(公告)号：US09012281B2

公开(公告)日：2015-04-21

申请号：US13829703

申请日：2013-03-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Dae Suk ,  Hee-Soo Kang ,  Sung-Il Park ,  Sang-Hoon Lee

IPC: H01L21/8238 ,  H01L27/092

CPC classification number: H01L27/0922 ,  H01L21/823871

Abstract: A semiconductor device includes a substrate having a first region and a second region, first and second gate electrodes disposed on the first and second regions, respectively, and first and second source/drain regions disposed on at least one side of the first and second gate electrodes, respectively. The device further includes first and second silicide regions in the first and second source/drain regions, respectively. A contact area between the first silicide region and the first source/drain region is differs in size from a contact area between the second silicide region and the second source/drain region. Methods of fabricating such devices are also provided.

Abstract translation: 半导体器件包括具有第一区域和第二区域的衬底，分别设置在第一和第二区域上的第一和第二栅极电极以及设置在第一和第二栅极的至少一侧上的第一和第二源极/漏极区域 电极。 该器件还分别包括第一和第二源极/漏极区域中的第一和第二硅化物区域。 第一硅化物区域和第一源极/漏极区域之间的接触区域的大小与第二硅化物区域和第二源极/漏极区域之间的接触面积不同。 还提供了制造这种装置的方法。