中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

34 records (took 0.022 seconds)

    SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME
    4.
    发明申请
    SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME 有权
    半导体器件及其制造方法

    公开(公告)号：US20140203348A1

    公开(公告)日：2014-07-24

    申请号：US14162481

    申请日：2014-01-23

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sung-Dae Suk ,  Heesoo Kang ,  Sungil Park ,  Changwoo Oh

    IPC: H01L29/06 ,  H01L29/78

    CPC classification number: H01L21/764 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

    Abstract: Provided is a semiconductor device, which includes a gate electrode crossing over a semiconductor fin disposed on a substrate, a gate dielectric layer disposed between the gate electrode and the semiconductor fin, a channel region having a three dimensional structure defined in the semiconductor fin under the gate electrode, impurity regions disposed in the semiconductor fin at both sides of the gate electrode and spaced apart from the gate electrode, a first interlayer dielectric layer covering an entire surface of the substrate, except for the gate electrode, first contact plugs passing through the first interlayer dielectric layer and contacting the impurity regions, and a second interlayer dielectric layer covering the gate electrode and partially filling a space between the gate electrode and the impurity regions to define an air gap between the gate electrode and the impurity regions.

    Abstract translation: 提供了一种半导体器件，其包括跨越设置在衬底上的半导体翅片上的栅极电极，设置在栅极电极和半导体鳍片之间的栅极电介质层，具有限定在半导体鳍片下方的三维结构的沟道区域 栅极电极，设置在栅电极两侧并与栅电极间隔开的半导体鳍片中的杂质区域，除了栅电极之外覆盖基板整个表面的第一层间电介质层，穿过第 第一层间电介质层和与杂质区接触的第二层间电介质层和覆盖栅电极并部分地填充栅电极和杂质区之间的空间的第二层间电介质层，以限定栅电极和杂质区之间的气隙。

    Semiconductor device
    5.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US11251312B2

    公开(公告)日：2022-02-15

    申请号：US16395907

    申请日：2019-04-26

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Mongsong Liang ,  Sung-Dae Suk ,  Geumjong Bae

    IPC: H01L29/423 ,  H01L29/786 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/11 ,  H01L29/06 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66 ,  H01L29/78

    Abstract: A semiconductor device includes a first transistor, a second transistor and a third transistor provided on a substrate, the first to third transistors respectively including source and drain regions spaced apart from each other, a gate structure extending in a first direction on the substrate and interposed between the source and drain regions, and a channel region connecting the source and drain regions to each other. A channel region of the second transistor and a channel region of the third transistor respectively include a plurality of channel portions, the plurality of channel portions spaced apart from each other in a second direction, perpendicular to an upper surface of the substrate, and connected to the source and drain regions, respectively. A width of a channel portion of the third transistor in the first direction is greater than a width of a channel portion of the second transistor in the first direction.

    Semiconductor device
    6.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US10304964B2

    公开(公告)日：2019-05-28

    申请号：US15238059

    申请日：2016-08-16

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Mongsong Liang ,  Sung-Dae Suk ,  Guemjong Bae

    IPC: H01L29/786 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/11 ,  H01L29/06 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

    Abstract: A semiconductor device includes a first transistor, a second transistor and a third transistor provided on a substrate, the first to third transistors respectively including source and drain regions spaced apart from each other, a gate structure extending in a first direction on the substrate and interposed between the source and drain regions, and a channel region connecting the source and drain regions to each other. A channel region of the second transistor and a channel region of the third transistor respectively include a plurality of channel portions, the plurality of channel portions spaced apart from each other in a second direction, perpendicular to an upper surface of the substrate, and connected to the source and drain regions, respectively. A width of a channel portion of the third transistor in the first direction is greater than a width of a channel portion of the second transistor in the first direction.

    Semiconductor device
    7.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US10109631B2

    公开(公告)日：2018-10-23

    申请号：US15438113

    申请日：2017-02-21

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sung-Dae Suk ,  Jongho Lee ,  Geumjong Bae

    IPC: H01L27/092 ,  H01L23/535 ,  H01L29/78 ,  H01L29/417

    Abstract: A semiconductor device includes an insulating layer on a substrate, a channel region on the insulating layer, a gate structure on the insulating layer, the gate structure crossing the channel region, source/drain regions on the insulating layer, the source/drain regions being spaced apart from each other with the gate structure interposed therebetween, the channel region connecting the source/drain regions to each other, and contact plugs connected to the source/drain regions, respectively. The channel region includes a plurality of semiconductor patterns that are vertically spaced apart from each other on the insulating layer, the insulating layer includes first recess regions that are adjacent to the source/drain regions, respectively, and the contact plugs include lower portions provided into the first recess regions, respectively.

    Method of fabricating semiconductor device
    9.
    发明授权
    Method of fabricating semiconductor device 有权
    制造半导体器件的方法

    公开(公告)号：US09412849B1

    公开(公告)日：2016-08-09

    申请号：US14966174

    申请日：2015-12-11

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sung-Dae Suk ,  Dong-Il Bae

    IPC: H01L21/00 ,  H01L29/66 ,  H01L29/423 ,  H01L21/02 ,  H01L21/308 ,  H01L29/06 ,  H01L21/84 ,  H01L21/311

    CPC classification number: H01L29/66795 ,  B82Y10/00 ,  H01L21/02532 ,  H01L21/308 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696

    Abstract: A method of fabricating a semiconductor device includes forming first and second fin-type structures on first and second regions of a substrate, respectively, forming first and second capping layers on the first and second fin-type structures, respectively, forming a first dummy gate electrode on the first capping layer and a second dummy gate electrode on the second capping layer, exposing the first capping layer and the second capping layer by removing the first dummy gate electrode and the second dummy gate electrode, forming a second wire pattern group on the second region, and forming a first wire pattern group on the first region.

    Abstract translation: 一种制造半导体器件的方法包括分别在衬底的第一和第二区域上形成第一和第二鳍式结构，分别在第一和第二鳍式结构上形成第一和第二覆盖层，形成第一虚拟栅极 第一盖层上的电极和第二封盖层上的第二虚拟栅极电极，通过去除第一虚拟栅极电极和第二虚拟栅极电极来暴露第一覆盖层和第二覆盖层，在第二覆盖层上形成第二引线图案组 并且在所述第一区域上形成第一线图案组。

    Gate All Around Semiconductor Device
    10.
    发明申请
    Gate All Around Semiconductor Device 审中-公开
    门全周用半导体器件

    公开(公告)号：US20140225169A1

    公开(公告)日：2014-08-14

    申请号：US13832017

    申请日：2013-03-15

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sung-Dae Suk ,  Dae-Won Ha ,  Su-Yeon Park

    IPC: H01L29/78

    CPC classification number: H01L29/42392 ,  H01L29/66545 ,  H01L29/785 ,  H01L29/78696

    Abstract: A gate all around (GAA) type semiconductor device is provided. The GAA type semiconductor device includes source/drain layers formed to be spaced apart from each other, a channel layer connecting the source/drain layers, and a gate electrode formed along the periphery of at least a portion of the channel layer, wherein lower portions of the source/drain layers are formed more deeply than the channel layer, and an insulation pattern is formed between the lower portions of the source/drain layers and lower portions of the gate electrode.

    Abstract translation: 提供了全封闭（GAA）型半导体器件。 GAA型半导体器件包括形成为彼此间隔开的源极/漏极层，连接源极/漏极层的沟道层以及沿着沟道层的至少一部分的周边形成的栅电极，其中下部 源极/漏极层的沟道层比沟道层更深地形成，并且在源/漏层的下部和栅电极的下部之间形成绝缘图案。

Patent Agency Ranking