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公开(公告)号：US11532370B1
公开(公告)日：2022-12-20
申请号：US17329304
申请日：2021-05-25
Applicant: SanDisk Technologies LLC
Inventor： Xiang Yang , Huai-Yuan Tseng , Deepanshu Dutta
IPC: G11C11/34 , G11C16/34 , G11C16/10 , G11C16/26 , G11C11/56 , H01L27/11565 , G11C16/04 , H01L25/065 , H01L27/11582
Abstract: To improve programming performance for a non-volatile memory , the verification of multiple programming levels can be performed based on a single discharge of a sensing capacitor through a selected memory cell by using different voltage levels on a second plate of the sensing capacitor: after discharging a first plate of the sensing capacitor through the selected memory cell, a result amount of charge is trapped on the first plate, which is then used to set first and second control gate voltages on a sensing transistor whose control gate is connected to the first place of the sensing capacitor based on respectively setting the second plate of the sensing capacitor to first and second voltage levels. To further improve programming performance, when the non-volatile memory stores in a multistate format, after the next to highest data state finishes programming, the next programming pulse can use a larger step size.
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公开(公告)号：US20220310179A1
公开(公告)日：2022-09-29
申请号：US17212871
申请日：2021-03-25
Applicant: SanDisk Technologies LLC
Inventor： Fanqi Wu , Deepanshu Dutta , Huai-Yuan Tseng
IPC: G11C16/34 , G11C16/16 , G11C16/04 , H01L27/11524 , H01L27/11529 , H01L27/11556 , H01L27/1157 , H01L27/11573 , H01L27/11582
Abstract: A method of performing an erase operation on non-volatile storage is disclosed. The method comprises: applying, in a first erase loop of a plurality of erase loops of the erase operation, a first erase pulse to a first grouping of non-volatile storage elements; after applying the first erase pulse, determining an upper tail of a threshold voltage distribution of the first grouping of non-volatile storage elements; determining a difference between the upper tail of the first grouping of non-volatile storage elements and an upper tail of a threshold voltage distribution of a second grouping of non-volatile storage elements; and disabling, in a second erase loop of the plurality of erase loops, the erase operation on the first grouping of non-volatile storage elements if the difference is greater than or equal to the threshold amount.
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公开(公告)号：US11437110B1
公开(公告)日：2022-09-06
申请号：US17212871
申请日：2021-03-25
Applicant: SanDisk Technologies LLC
Inventor： Fanqi Wu , Deepanshu Dutta , Huai-Yuan Tseng
IPC: G11C16/00 , G11C16/34 , G11C16/16 , G11C16/04 , H01L27/11524 , H01L27/11582 , H01L27/11556 , H01L27/1157 , H01L27/11573 , H01L27/11529
Abstract: A method of performing an erase operation on non-volatile storage is disclosed. The method comprises: applying, in a first erase loop of a plurality of erase loops of the erase operation, a first erase pulse to a first grouping of non-volatile storage elements; after applying the first erase pulse, determining an upper tail of a threshold voltage distribution of the first grouping of non-volatile storage elements; determining a difference between the upper tail of the first grouping of non-volatile storage elements and an upper tail of a threshold voltage distribution of a second grouping of non-volatile storage elements; and disabling, in a second erase loop of the plurality of erase loops, the erase operation on the first grouping of non-volatile storage elements if the difference is greater than or equal to the threshold amount.
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公开(公告)号：US11315648B2
公开(公告)日：2022-04-26
申请号：US16915663
申请日：2020-06-29
Applicant: SanDisk Technologies LLC
Inventor： Yu-Chung Lien , Dengtao Zhao , Huai-Yuan Tseng
Abstract: An apparatus includes a memory controller configured to apply selected one or ones of the program verify voltage levels to a single tier of memory cells. A memory controller is configured to: program data into the plurality of memory cells; and perform a program verify operation across multiple voltage levels with a first voltage level of the program verify operation being applied to a single tier that represents all of the tiers in the memory group and a second voltage level of the program verify operation being applied to multiple tiers, wherein the first voltage level is less than the second voltage level. In embodiments, less than all of the tiers, e.g., two or four tiers, can be used in the program verify to represent all of the tires.
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公开(公告)号：US20220101926A1
公开(公告)日：2022-03-31
申请号：US17034086
申请日：2020-09-28
Applicant: SANDISK TECHNOLOGIES LLC
Inventor： Ken Oowada , Huai-Yuan Tseng
Abstract: To improve the erase process, multiple methods of erasing are utilized. A first method of erasing is relied on at the beginning of life of the memory system. A second method is increasingly relied on as the memory system is used and undergoes many program/erase cycles. In one example, the first method of erase includes applying an erase enable voltage separately to different subsets of the word lines while word lines not receiving the erase enable voltage receive an erase inhibit voltage. In one example, the second method of erase includes applying an erase enable voltage concurrently to all subsets of the word lines.
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Patent Agency Ranking
36.发明授权公开(公告)号：US11226772B1
公开(公告)日：2022-01-18
申请号：US16912381
申请日：2020-06-25
Applicant: SanDisk Technologies LLC
Inventor： Yu-Chung Lien , Mark Murin , Hua-Ling Cynthia Hsu , Tomer Eliash , Huai-Yuan Tseng , Deepanshu Dutta
IPC: G06F3/06 , G11C16/10 , G11C16/32 , H01L25/065 , G11C16/04
Abstract: Power and/or current regulation in non-volatile memory systems is disclosed. Peak power/current usage may be reduced by staggering concurrent program operations in the different semiconductor dies. Each set of one or more semiconductor dies has an earliest permitted start time for its program operation, as well as a number of permitted backup start times. The permitted start times are unique for each set of one or more semiconductor dies. There may be a uniform gap or delay between each permitted start time. If a semiconductor die is busy with another memory operation at or after its earliest permitted start time, then the program operation is initiated or resumed at one of the permitted backup times. By having permitted backup times, the memory system need not poll each semiconductor die to determine whether the semiconductor die is ready/busy in order to determine when a die should start a program operation.
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公开(公告)号：US20210407596A1
公开(公告)日：2021-12-30
申请号：US16912917
申请日：2020-06-26
Applicant: SanDisk Technologies LLC
Inventor： Yu-Chung Lien , Hua-Ling Hsu , Huai-Yuan Tseng
Abstract: An apparatus, disclosed herein, comprises a plurality of planes, each plane of the plurality of planes including a plurality of memory cells and a control circuit coupled to the plurality of memory cells. The control circuit is configured to: determine a position of a program loop in a sequence of program loops performed to complete a programming operation; initiate an inhibit bit line ramping event for the first plane including ramping of a set of bit lines of a first plane up to an inhibit voltage and based on the position of the program loop, initiate an inhibit bit line ramping event with a ramping start time delay for a second plane, where the inhibit bit line ramping event for the second plane includes initiating ramping of a set of bit lines of the second plane up to the inhibit voltage after the ramping start time delay.
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公开(公告)号：US11211127B1
公开(公告)日：2021-12-28
申请号：US16912917
申请日：2020-06-26
Applicant: SanDisk Technologies LLC
Inventor： Yu-Chung Lien , Hua-Ling Hsu , Huai-Yuan Tseng
IPC: G11C11/56 , G11C16/04 , G11C16/10 , G11C16/24 , G11C16/32 , H01L27/11582 , H01L27/11519 , H01L27/11565 , H01L27/11556
Abstract: An apparatus, disclosed herein, comprises a plurality of planes, each plane of the plurality of planes including a plurality of memory cells and a control circuit coupled to the plurality of memory cells. The control circuit is configured to: determine a position of a program loop in a sequence of program loops performed to complete a programming operation; initiate an inhibit bit line ramping event for the first plane including ramping of a set of bit lines of a first plane up to an inhibit voltage and based on the position of the program loop, initiate an inhibit bit line ramping event with a ramping start time delay for a second plane, where the inhibit bit line ramping event for the second plane includes initiating ramping of a set of bit lines of the second plane up to the inhibit voltage after the ramping start time delay.
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公开(公告)号：US20210327520A1
公开(公告)日：2021-10-21
申请号：US16854030
申请日：2020-04-21
Applicant: SanDisk Technologies LLC
Inventor： Xue Pitner , Deepanshu Dutta , Huai-Yuan Tseng , Ravi Kumar , Cynthia Hsu
Abstract: A storage device is disclosed herein. The storage device comprises a block including a plurality of memory cells and a circuit coupled to the plurality of memory cells of the block. The circuit is configured to program memory cells of a plurality of strings of a word line of the block and verify, for a plurality of sets of the memory cells, a data state of a set of the memory cells, where each set of the plurality of sets of the memory cells includes a memory cell from each string of the plurality of strings of the word line. Further, the circuit is configured to determine a number of sets of the plurality of memory cell sets that are verified to be in a first data state and determine, based on the number of sets, whether the block is faulty.
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公开(公告)号：US20210257037A1
公开(公告)日：2021-08-19
申请号：US16793749
申请日：2020-02-18
Applicant: SanDisk Technologies LLC
Inventor： Zhiping Zhang , Huai-Yuan Tseng , Dengtao Zhao , Deepanshu Dutta
Abstract: A method for memory program verification includes performing a write operation on memory cells of a memory device. The method also includes identifying memory strings associated with respective memory cells of the memory cells. The method also includes identifying a first memory string of the memory strings. The method also includes disabling a portion of a write verification for the first memory string. The method also includes enabling the portion of the write verification for other memory strings of the memory strings. The method also includes performing at least the portion of the write verification operation on write verification enabled memory strings.
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