公开(公告)号：US10200058B1

公开(公告)日：2019-02-05

申请号：US15961296

申请日：2018-04-24

Applicant: SanDisk Technologies LLC

Inventor： Won Ho Choi

IPC: H03M1/12 ,  G11C11/16 ,  H01F10/32 ,  H01L27/22 ,  H01L43/08

Abstract: Analog-to-digital conversion circuits are presented which employ magnetic tunnel junction (MTJ) elements that change state probabilistically in response to application of electrical pulses. Some implementations form a multi-channel analog-to-digital conversion circuit, with each channel comprising a magnetic tunnel junction (MTJ) element, and a pulse generator that determines characteristics of perturbation pulses to be applied to an MTJ element based at least on an analog input. The pulse generator also applies read pulses to the MTJ element to produce indications of magnetization state changes for the MTJ element due to application of the perturbation pulses. Each channel of the multi-channel analog-to-digital conversion circuit can include count circuitry that counts the indications of the magnetization state changes for an associated MTJ element. Outputs from each single-channel analog-to-digital converter are combined to determine a digital output representative of the analog input.

公开(公告)号：US10026478B1

公开(公告)日：2018-07-17

申请号：US15448602

申请日：2017-03-03

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Won Ho Choi ,  Jay Kumar ,  Zvonimir Bandic

IPC: G11C13/00

Abstract: Systems and methods for improving the performance of a non-volatile memory array during a memory operation by concurrently applying two different selected word line voltages to two different word lines within the non-volatile memory array are described. The memory operation may comprise a write operation or a combination of SET and RESET operations. The memory array may include a first word line connected to a first set of memory cells, a second word line connected to a second set of memory cells, and a third word line connected to a third set of memory cells. During the memory operation, the first word line may be set to a first selected word line voltage (e.g., 3V), the second word line may be set to a second selected word line voltage (e.g., 0V), and the third word line may be set to an unselected word line voltage (e.g., 1.5V).

公开(公告)号：US11657259B2

公开(公告)日：2023-05-23

申请号：US16722580

申请日：2019-12-20

Applicant: SanDisk Technologies LLC

Inventor： Tung Thanh Hoang ,  Won Ho Choi ,  Martin Lueker-Boden

IPC: G06N3/04 ,  G06N3/063 ,  G11C13/00 ,  G06F7/523 ,  G11C11/54 ,  G06N3/08

CPC classification number: G06N3/063 ,  G06F7/523 ,  G06N3/04 ,  G11C11/54 ,  G11C13/004 ,  G11C13/0069 ,  G06N3/08

Abstract: Techniques are presented for performing in-memory matrix multiplication operations for binary input, binary weight valued convolution neural network (CNN) inferencing. The weights of a filter are stored in pairs of memory cells of a storage class memory device, such as a ReRAM or phase change memory based devices. To reduce current consumption, the binary valued filters are transformed into ternary valued filters by taking sums and differences of binary valued filter pairs. The zero valued weights of the transformed filters are stored as a pair of high resistance state memory cells, reducing current consumption during convolution. The results of the in-memory multiplications are pair-wise combined to compensate for the filter transformations. To compensate for zero valued weights, a zero weight register stores the number of zero weights along each bit line and is used to initialize counter values for accumulating the multiplication operations.

公开(公告)号：US11625586B2

公开(公告)日：2023-04-11

申请号：US16653365

申请日：2019-10-15

Applicant: SanDisk Technologies LLC

Inventor： Tung Thanh Hoang ,  Won Ho Choi ,  Martin Lueker-Boden

IPC: G06N3/063 ,  G06F17/18

Abstract: Use of a NAND array architecture to realize a binary neural network (BNN) allows for matrix multiplication and accumulation to be performed within the memory array. A unit synapse for storing a weight of a BNN is stored in a pair of series connected memory cells. A binary input is applied on a pair of word lines connected to the unit synapse to perform the multiplication of the input with the weight. The results of such multiplications are determined by a sense amplifier, with the results accumulated by a counter. The arrangement extends to ternary inputs to realize a ternary-binary network (TBN) by adding a circuit to detect 0 input values and adjust the accumulated count accordingly. The arrangement further extends to a ternary-ternary network (TTN) by allowing 0 weight values in a unit synapse, maintaining the number of 0 weights in a register, and adjusting the count accordingly.

公开(公告)号：US11515472B2

公开(公告)日：2022-11-29

申请号：US17109291

申请日：2020-12-02

Applicant: SanDisk Technologies LLC

Inventor： Young-Suk Choi ,  Won Ho Choi

IPC: G11C7/00 ,  G11C11/14 ,  H01L43/02 ,  H01L43/08 ,  H01L27/22 ,  G11C11/16 ,  G06N3/063 ,  G06N3/04 ,  G11C11/00 ,  G11C11/54 ,  G11C11/401

Abstract: Apparatuses, systems, and methods are disclosed for magnetoresistive random access memory. A magnetic tunnel junction (MTJ) for storing data may include a reference layer. A free layer of an MTJ may be separated from a reference layer by a barrier layer. A free layer may be configured such that one or more resistance states for an MTJ correspond to one or more positions of a magnetic domain wall within the free layer. A domain stabilization layer may be coupled to a portion of a free layer, and may be configured to prevent migration of a domain wall into the portion of the free layer.

公开(公告)号：US11328204B2

公开(公告)日：2022-05-10

申请号：US16368347

申请日：2019-03-28

Applicant: SanDisk Technologies LLC

Inventor： Won Ho Choi ,  Pi-Feng Chiu ,  Wen Ma ,  Minghai Qin ,  Gerrit Jan Hemink ,  Martin Lueker-Boden

IPC: G11C16/04 ,  G06N3/04 ,  G11C11/56 ,  G11C13/00 ,  G11C11/16 ,  G06N3/08 ,  G06N3/063 ,  G11C16/26

Abstract: Use of a NAND array architecture to realize a binary neural network (BNN) allows for matrix multiplication and accumulation to be performed within the memory array. A unit synapse for storing a weight of a BNN is stored in a pair of series connected memory cells. A binary input is applied as a pattern of voltage values on a pair of word lines connected to the unit synapse to perform the multiplication of the input with the weight by determining whether or not the unit synapse conducts. The results of such multiplications are determined by a sense amplifier, with the results accumulated by a counter.

公开(公告)号：US20210181979A1

公开(公告)日：2021-06-17

申请号：US16717468

申请日：2019-12-17

Applicant: SanDisk Technologies LLC

Inventor： Won Ho Choi ,  Ward Parkinson ,  Raj Ramanujan ,  Martin Lueker-Boden

IPC: G06F3/06 ,  G11C13/00

Abstract: Apparatuses and techniques are described for reading crosspoint arrays of memory cells with high bandwidth and a relatively small page buffer. Multiple crosspoint arrays (XPAs) are read in parallel, with one memory cell per XPA being read, in a bank of XPAs. To reduce the read time, a row can be selected for the XPAs, after which memory cells in different columns are read, one column at a time, while the same row is selected. This avoids the need to transmit commands and a row address for re-selecting the row in each successive read operation. The XPAs may be ungrouped, or one XPA may be accessible at a time in a group. In one option, the XPAs are arranged in sets, either individually or in groups, and one set is accessible at a time.

公开(公告)号：US20210110244A1

公开(公告)日：2021-04-15

申请号：US16653365

申请日：2019-10-15

Applicant: SanDisk Technologies LLC

Inventor： Tung Thanh Hoang ,  Won Ho Choi ,  Martin Lueker-Boden

IPC: G06N3/063 ,  G06F17/18

Abstract: Use of a NAND array architecture to realize a binary neural network (BNN) allows for matrix multiplication and accumulation to be performed within the memory array. A unit synapse for storing a weight of a BNN is stored in a pair of series connected memory cells. A binary input is applied on a pair of word lines connected to the unit synapse to perform the multiplication of the input with the weight. The results of such multiplications are determined by a sense amplifier, with the results accumulated by a counter. The arrangement extends to ternary inputs to realize a ternary-binary network (TBN) by adding a circuit to detect 0 input values and adjust the accumulated count accordingly. The arrangement further extends to a ternary-ternary network (TTN) by allowing 0 weight values in a unit synapse, maintaining the number of 0 weights in a register, and adjusting the count accordingly.

公开(公告)号：US20200075099A1

公开(公告)日：2020-03-05

申请号：US16253980

申请日：2019-01-22

Applicant: SanDisk Technologies LLC

Inventor： Won Ho Choi ,  Jongyeon Kim

IPC: G11C15/02 ,  G11C7/10 ,  H01L27/22 ,  H01L43/10 ,  H01L43/06

Abstract: Ternary content addressable memory (TCAM) circuits are provided herein. In one example implementation, a TCAM circuit can include a first spin-orbit torque (SOT) magnetic tunnel junction (MTJ) element having a pinned layer coupled to a first read transistor controlled by a first search line, and having a spin hall effect (SHE) layer coupled in a first configuration across complemented write inputs. The TCAM circuit can include a second SOT MTJ element having a pinned layer coupled to a second read transistor controlled by a second search line, and having a SHE layer coupled in a second configuration across the complemented write inputs. The TCAM circuit can include a bias transistor configured to provide a bias voltage to drain terminals of the first read transistor and the second read transistor, and a voltage keeper element that couples the drain terminals to a match indicator line.

公开(公告)号：US20200034686A1

公开(公告)日：2020-01-30

申请号：US16405178

申请日：2019-05-07

Applicant: SanDisk Technologies LLC

Inventor： Pi-Feng Chiu ,  Won Ho Choi ,  Wen Ma ,  Martin Lueker-Boden

IPC: G06N3/04 ,  G11C11/56 ,  G11C13/00 ,  G11C11/16 ,  G06N3/08

Abstract: Use of a non-volatile memory array architecture to realize a neural network (BNN) allows for matrix multiplication and accumulation to be performed within the memory array. A unit synapse for storing a weight of a neural network is formed by a differential memory cell of two individual memory cells, such as a memory cells having a programmable resistance, each connected between a corresponding one of a word line pair and a shared bit line. An input is applied as a pattern of voltage values on word line pairs connected to the unit synapses to perform the multiplication of the input with the weight by determining a voltage level on the shared bit line. The results of such multiplications are determined by a sense amplifier, with the results accumulated by a summation circuit.