公开(公告)号：US20230055062A1

公开(公告)日：2023-02-23

申请号：US17796903

申请日：2021-02-08

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yuki OKAMOTO ,  Munehiro KOZUMA ,  Tatsuya ONUKI

IPC: G06F7/544 ,  H01L27/108 ,  H01L27/12 ,  H01L29/786

Abstract: A semiconductor device with a novel structure is provided. A plurality of memory circuits, a switching circuit, and an arithmetic circuit are included. Each of the plurality of memory circuits has a function of retaining weight data and a function of outputting the weight data to a first wiring. The switching circuit has a function of switching a conduction state between any one of the plurality of first wirings and a second wiring. The arithmetic circuit has a function of performing arithmetic processing using input data and the weight data supplied to the second wiring. The memory circuits are provided in a first layer. The switching circuit and the arithmetic circuit are provided in a second layer. The first layer is provided in a layer different from the second layer.

公开(公告)号：US20220366958A1

公开(公告)日：2022-11-17

申请号：US17618993

申请日：2020-06-09

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Fumika AKASAWA ,  Munehiro KOZUMA

IPC: G11C11/405 ,  H01L27/108 ,  H01L27/12 ,  H01L29/786

Abstract: Since power source voltages are different depending on circuits used for devices, a circuit for outputting at least two or more power sources is additionally prepared. An object is to unify outputs of the power source voltages. A transistor using an oxide semiconductor is provided in such a manner that electrical charge is retained in a node where the transistor and a capacitor are electrically connected to each other, a reset signal is applied to a gate of the transistor to switch the states of the transistor from off to on, and the node is reset when the transistor is on. A circuit configuration that generates and utilizes a potential higher than or equal to a potential of a single power source can be achieved.

公开(公告)号：US20220343954A1

公开(公告)日：2022-10-27

申请号：US17640452

申请日：2020-09-08

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Takeshi AOKI ,  Munehiro KOZUMA ,  Masashi FUJITA ,  Takahiko ISHIZU

IPC: G11C7/06 ,  G11C7/08 ,  G11C11/4091 ,  G11C11/54

Abstract: A semiconductor device in which energy required for data transfer between an arithmetic device and a memory is reduced is provided. The semiconductor device includes a peripheral circuit and a memory cell array. The peripheral circuit has a function of a driver circuit and a control circuit for the memory cell array, and an arithmetic function. The peripheral circuit includes a sense amplifier circuit and an arithmetic circuit, and the memory cell array includes a memory cell and a bit line. The sense amplifier circuit has a function of determining whether the bit line is at a high level or a low level, and outputs the result to the arithmetic circuit. The arithmetic circuit has a function of performing a product-sum operation, the result of which is output from the semiconductor device.

公开(公告)号：US20220276834A1

公开(公告)日：2022-09-01

申请号：US17625392

申请日：2020-06-29

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Takeshi AOKI ,  Yoshiyuki KUROKAWA ,  Munehiro KOZUMA ,  Takuro KANEMURA

IPC: G06F7/544 ,  H01L27/108 ,  H01L27/12 ,  H01L29/786 ,  G11C11/405 ,  G11C11/408 ,  G11C11/4094 ,  G11C11/4096

Abstract: A semiconductor device which can efficiently perform reading of a weight coefficient and a product-sum operation is provided. The semiconductor device includes a product-sum operation circuit and a memory device. The product-sum operation circuit is formed using transistors formed on a semiconductor substrate, and a memory cell of the memory device is formed using an OS transistor provided to be stacked above the semiconductor substrate. The semiconductor device includes a plurality of product-sum operation units where the product-sum operation circuit and the memory cell of the memory device are electrically connected to each other. In each of the product-sum operation units, a weight coefficient stored in the memory cell can be read and a product-sum operation can be performed.

公开(公告)号：US20220262953A1

公开(公告)日：2022-08-18

申请号：US17628091

申请日：2020-07-27

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Munehiro KOZUMA ,  Takahiko ISHIZU ,  Takeshi AOKI ,  Masashi FUJITA ,  Kazuma FURUTANI ,  Kousuke SASAKI

IPC: H01L29/786 ,  H01L27/108 ,  G11C7/10 ,  G11C7/12 ,  G11C7/14 ,  G06F7/544

Abstract: A semiconductor device having a novel structure is provided. The semiconductor device includes a CPU and an accelerator. The accelerator includes a first memory circuit and an arithmetic circuit. The first memory circuit includes a first transistor. The first transistor includes a semiconductor layer containing a metal oxide in a channel formation region. The arithmetic circuit includes a second transistor. The second transistor includes a semiconductor layer containing silicon in a channel formation region. The first transistor and the second transistor are provided to be stacked. The CPU includes a CPU core including a flip-flop provided with a backup circuit. The backup circuit includes a third transistor. The third transistor includes a semiconductor layer containing a metal oxide in a channel formation region.

公开(公告)号：US20220254401A1

公开(公告)日：2022-08-11

申请号：US17617969

申请日：2020-06-08

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Yoshiyuki KUROKAWA ,  Munehiro KOZUMA ,  Takeshi AOKI

IPC: G11C11/405 ,  H01L27/108 ,  H01L27/12 ,  H01L29/786 ,  G01N33/00 ,  G01V3/02

Abstract: A semiconductor device resistant to a high temperature with low power consumption is provided. The semiconductor device includes a first and a second circuit, a first and a second cell, and a first and a second wiring. The first cell includes a first transistor, and the second cell includes a second transistor. The first and the second transistor operate in a subthreshold region. The first cell is electrically connected to the first circuit through the first wiring, the first cell is electrically connected to the second circuit through the second wiring, and the second cell is electrically connected to the second circuit through the second wiring. The first cell sets a current flowing through the first transistor to a first current and the second cell sets a current flowing through the second transistor to a second current. At this time, a potential corresponding to the second current is input from the second wiring to the first cell. Then, a third current flows from the second circuit to change a potential of the second wiring, whereby the first cell outputs a fourth current corresponding to the amount of the potential change and the first current.

公开(公告)号：US20220190398A1

公开(公告)日：2022-06-16

申请号：US17439436

申请日：2020-03-16

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takayuki IKEDA ,  Takeshi AOKI ,  Munehiro KOZUMA ,  Kei TAKAHASHI ,  Shunpei YAMAZAKI

IPC: H01M10/42

Abstract: A semiconductor device with reduced power consumption is provided. With three transistors, potentials of two nodes are switched and a voltage is detected. One of a source and a drain of a first transistor is electrically connected to a first terminal. The other of the source and the drain of the first transistor is electrically connected to a non-inverting input of a comparator through a first node. One of a source and a drain of a second transistor is electrically connected to a second terminal. The other of the source and the drain of the second transistor is electrically connected to one of a source and a drain of a third transistor through a second node. The other of the source and the drain of the third transistor is electrically connected to a third terminal. A first capacitor is provided between the first node and the second node. An inverting input of the comparator is electrically connected to a fourth terminal. An output of the comparator is electrically connected to a fifth terminal.

公开(公告)号：US20210249703A1

公开(公告)日：2021-08-12

申请号：US16973666

申请日：2019-07-03

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Takayuki IKEDA ,  Munehiro KOZUMA ,  Takanori MATSUZAKI ,  Ryota TAJIMA ,  Shunpei YAMAZAKI

IPC: H01M10/44 ,  H01L27/105 ,  H01L27/12 ,  H01L29/24 ,  H01L29/786 ,  H02J7/00 ,  H01M10/48

Abstract: A semiconductor device capable of charging that is less likely to cause deterioration of a power storage device is provided.
The amount of a charging current is adjusted in accordance with the ambient temperature. Charging under low-temperature environments is performed with a reduced charging current. When the ambient temperature is too low or too high, the charging is stopped. Measurement of the ambient temperature is performed with a memory element using an oxide semiconductor. The use of a memory element using an oxide semiconductor enables measurement of the ambient temperature and retention of the temperature information to be performed at the same time.

公开(公告)号：US20200343245A1

公开(公告)日：2020-10-29

申请号：US16765398

申请日：2018-11-22

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei YAMAZAKI ,  Hajime KIMURA ,  Munehiro KOZUMA ,  Takeshi AOKI ,  Hiroki INOUE ,  Shintaro HARADA ,  Daisuke MATSUBAYASHI

IPC: H01L27/105 ,  H01L27/12 ,  H01L23/34 ,  H01L29/786

Abstract: Provided is a storage device that achieves both retention operation at high temperatures and high-speed operation at low temperatures.The storage device includes a driver circuit and a plurality of memory cells, and the memory cell includes a transistor and a capacitor; the transistor includes a metal oxide in a channel formation region. In the case where the transistor includes a first gate and a second gate, the driver circuit has a function of driving the second gate, and the driver circuit outputs a potential corresponding to the temperature of the storage device or the temperature of an environment where the storage device is placed to the second gate in a period during which the memory cell retains data.

公开(公告)号：US20180109835A1

公开(公告)日：2018-04-19

申请号：US15729191

申请日：2017-10-10

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Munehiro KOZUMA

IPC: H04N21/426 ,  H04N19/44 ,  G09G3/20 ,  H04N21/44

CPC classification number: H04N21/42607 ,  G09G3/2092 ,  G09G2300/0857 ,  G09G2310/08 ,  G09G2360/12 ,  H04N19/42 ,  H04N19/44 ,  H04N19/80 ,  H04N21/42692 ,  H04N21/44

Abstract: A semiconductor device that is suitable for high-speed operation is provided. The semiconductor device includes a decoder. The decoder includes a first circuit. The first circuit is configured to operate in synchronization with a clock signal. The first circuit is configured to perform image processing. A circuit configuration of the first circuit can be changed. Clock gating is performed on the first circuit to prevent the clock signal from being input to the first circuit when the circuit configuration of the first circuit is being changed. A broadcasting system including the semiconductor device is also provided.