公开(公告)号：US20250015614A1

公开(公告)日：2025-01-09

申请号：US18894219

申请日：2024-09-24

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Kei TAKAHASHI ,  Yuki OKAMOTO ,  Minato ITO ,  Takahiko ISHIZU ,  Hiroki INOUE ,  Shunpei YAMAZAKI

IPC: H02J7/00 ,  H01M10/42 ,  H01M10/44 ,  H03K3/0231 ,  H03K17/082

Abstract: A semiconductor device with reduced power consumption is provided. The semiconductor device includes a node ND1, a node ND2, a resistor, a capacitor, and a comparison circuit. The resistor is electrically connected in series between one of a positive electrode and a negative electrode of a secondary battery and a first terminal. The resistor has a function of converting current flowing between the one of the positive electrode and the negative electrode of the secondary battery and the first terminal into a first voltage. The first voltage is added to a voltage of the node ND2 through the capacitor. The comparison circuit has a function of comparing a voltage of the node ND1 and the voltage of the node ND2. The comparison circuit outputs a signal that notifies detection of overcurrent when the voltage of the node ND2 is higher than the voltage of the node ND1.

公开(公告)号：US20240332262A1

公开(公告)日：2024-10-03

申请号：US18740603

申请日：2024-06-12

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tatsuya ONUKI ,  Takanori MATSUZAKI ,  Yuki OKAMOTO ,  Shunpei YAMAZAKI

IPC: H01L25/065 ,  G11C5/06 ,  H01L23/00 ,  H01L29/786 ,  H10B12/00

CPC classification number: H01L25/0657 ,  G11C5/063 ,  H01L29/78693 ,  H10B12/315 ,  H10B12/50 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/1431 ,  H01L2924/1436

Abstract: A semiconductor device with a novel structure is provided. The semiconductor device includes a silicon substrate including a first circuit, a first element layer including a second circuit, and a second element layer including a third circuit. The first circuit includes a first transistor. The second circuit includes a second transistor. The third circuit includes a memory cell. The memory cell includes a third transistor and a capacitor. The first element layer and the second element layer constitute a stacked block stacked and provided in a direction perpendicular or substantially perpendicular to a surface of the silicon substrate. A plurality of stacked blocks are stacked and provided in the direction perpendicular or substantially perpendicular to the surface of the silicon substrate. Each of the plurality of stacked blocks includes a first wiring provided in the direction perpendicular or substantially perpendicular to the surface of the silicon substrate. The plurality of stacked blocks are electrically connected to each other through the wiring.

公开(公告)号：US20240321205A1

公开(公告)日：2024-09-26

申请号：US18569779

申请日：2022-06-23

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yuki OKAMOTO ,  Tatsuya ONUKI ,  Hidetomo KOBAYASHI ,  Munehiro KOZUMA ,  Takanori MATSUZAKI ,  Susumu KAWASHIMA ,  Yutaka OKAZAKI

IPC: G09G3/3233 ,  H01L27/088 ,  H01L27/12

CPC classification number: G09G3/3233 ,  H01L27/088 ,  H01L27/1225 ,  G09G2300/0426 ,  G09G2300/0852 ,  G09G2330/021

Abstract: The invention of the application is the invention regarding a semiconductor device and a method for driving the semiconductor device. The semiconductor device includes first and second transistors, first to fifth switches, first to third capacitors, and a display element. The first transistor (M2) comprises a back gate, a gate of the first transistor is electrically connected to the first switch (M1), the second switch (M3) and the first capacitor (C1) are positioned between the gate of the first transistor and a source of the first transistor, the back gate of the first transistor is electrically connected to the third switch (M4), the second capacitor (C2) is positioned between the back gate of the first transistor and the source of the first transistor, the source of the first transistor is electrically connected to the fourth switch (M6) and a drain of the second transistor (M5), a gate of the second transistor is electrically connected to the fifth switch (M7), the third capacitor (C3) is positioned between the gate of the second transistor and a source of the second transistor, and the source of the second transistor is electrically connected to the display element (61).

公开(公告)号：US20230176818A1

公开(公告)日：2023-06-08

申请号：US17922064

申请日：2021-05-10

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Minato ITO ,  Munehiro KOZUMA ,  Yuki OKAMOTO

IPC: G06F7/544 ,  G06N3/063 ,  H01L29/786 ,  H01L27/06

CPC classification number: G06F7/5443 ,  G06N3/063 ,  H01L29/7869 ,  H01L27/0688

Abstract: A semiconductor device with a novel structure is provided. The semiconductor device includes a storage circuit, an arithmetic circuit, and a driver circuit. The arithmetic circuit includes a switching circuit and a product-sum operation circuit. The storage circuit includes a first storage region and a second storage region. The first storage region has a function of retaining first storage data. The second storage region has a function of retaining second storage data. The switching circuit has a function of outputting the first storage data or the second storage data to the product-sum operation circuit. The driver circuit has a function of outputting first input data or second input data to the product-sum operation circuit. The product-sum operation circuit has a function of retaining first output data obtained by arithmetic processing performed on the first input data and the first storage data selected by the switching circuit. The arithmetic circuit has a function of adding, to the first output data, second output data obtained by arithmetic processing performed on the second input data and the second storage data selected by the switching circuit.

公开(公告)号：US20230055062A1

公开(公告)日：2023-02-23

申请号：US17796903

申请日：2021-02-08

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yuki OKAMOTO ,  Munehiro KOZUMA ,  Tatsuya ONUKI

IPC: G06F7/544 ,  H01L27/108 ,  H01L27/12 ,  H01L29/786

Abstract: A semiconductor device with a novel structure is provided. A plurality of memory circuits, a switching circuit, and an arithmetic circuit are included. Each of the plurality of memory circuits has a function of retaining weight data and a function of outputting the weight data to a first wiring. The switching circuit has a function of switching a conduction state between any one of the plurality of first wirings and a second wiring. The arithmetic circuit has a function of performing arithmetic processing using input data and the weight data supplied to the second wiring. The memory circuits are provided in a first layer. The switching circuit and the arithmetic circuit are provided in a second layer. The first layer is provided in a layer different from the second layer.

公开(公告)号：US20220021376A1

公开(公告)日：2022-01-20

申请号：US17312420

申请日：2019-12-11

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yuki OKAMOTO ,  Kei TAKAHASHI

IPC: H03K3/0233 ,  H03K17/22 ,  H03K19/0185 ,  H01M10/48 ,  H02J7/02

Abstract: To provide a hysteresis comparator having a small circuit area and low power consumption. The hysteresis comparator includes a comparator, a switch, a first capacitor, a second capacitor, and a logic circuit. A first terminal of the switch is electrically connected to one of a pair of conductive regions of the first capacitor, one of a pair of conductive regions of the second capacitor, and a first input terminal of the comparator. An output terminal of the comparator is electrically connected to an input terminal of the logic circuit. An output terminal of the logic circuit is electrically connected to the other of the pair of conductive regions of the second capacitor. The logic circuit has a function of generating an inverted signal of a signal input to the input terminal of the logic circuit and outputting the inverted signal to the output terminal of the logic circuit. A reference potential is input to the first input terminal of the comparator and the reference potential is held by the switch. Due to change in the potential of the output terminal of the comparator, the reference potential is changed by capacitive coupling of the second capacitor.

公开(公告)号：US20210159252A1

公开(公告)日：2021-05-27

申请号：US16625823

申请日：2018-06-15

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Yuki OKAMOTO ,  Yoshiyuki KUROKAWA ,  Naoto KUSUMOTO

IPC: H01L27/12 ,  H01L31/103 ,  H01L37/02 ,  H01L41/113 ,  H01L29/24 ,  H01L29/786 ,  H01L27/105

Abstract: A semiconductor device capable of retaining a signal sensed by a sensor element is provided. The semiconductor device includes a sensor element, a first transistor, a second transistor, and a third transistor. One electrode of the sensor element is electrically connected to a first gate. The first gate is electrically connected to one of a source and a drain of the third transistor. One of a source and a drain of the first transistor is electrically connected to a gate of the second transistor. A semiconductor layer includes a metal oxide.

公开(公告)号：US20180059841A1

公开(公告)日：2018-03-01

申请号：US15685792

申请日：2017-08-24

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takayuki IKEDA ,  Yuki OKAMOTO ,  Kei TAKAHASHI ,  Shunpei YAMAZAKI

IPC: G06F3/041 ,  G06F1/32

CPC classification number: G06F3/0412 ,  G02F1/13338 ,  G06F1/3203 ,  G06F1/3265 ,  G06F3/04883 ,  Y02D10/153

Abstract: A display device with excellent visibility can be provided. The display device includes a display region displayed by a light-emitting element. In the display region, a point touched by a user is a first point, a point which has been touched by the user prior to the first point is a second point, a vector that starts at the first point and ends at the second point is a first vector, a vector obtained by multiplying the first vector by k (k is a real number) is a second vector, and a point that is the second vector away from the first point is a third point, the display region includes a first region and a second region obtained by excluding the first region from the display region, The first region includes a first circle and a second circle, the center of the first circle is the first point, and the center of the second circle is the third point. The luminance in the first region is higher than the luminance in the second region.

公开(公告)号：US20170244398A1

公开(公告)日：2017-08-24

申请号：US15432002

申请日：2017-02-14

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yuki OKAMOTO ,  Yoshiyuki KUROKAWA

IPC: H03K5/24

CPC classification number: H03K5/2472 ,  G11C11/401 ,  G11C15/043 ,  H03M1/747

Abstract: A semiconductor device that enables a memory size reduction is provided. The semiconductor device includes a converter circuit, a memory circuit, and a detection circuit. The converter circuit has a function of converting first data that includes a digital voltage value to second data that includes an analog current value. The memory circuit has a function of storing third data that includes an analog current value. The detection circuit has a function of generating data that indicates whether the analog current values of the second and third data match.

公开(公告)号：US20160126888A1

公开(公告)日：2016-05-05

申请号：US14925161

申请日：2015-10-28

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yuki OKAMOTO ,  Yoshiyuki KUROKAWA

IPC: H03B5/12 ,  H03L7/099

CPC classification number: H03L7/099 ,  H01L27/1156 ,  H03K3/0315

Abstract: An object of the present invention is to provide a semiconductor device including an oscillator circuit including a circuit between inverters. In the circuit, a sum of the length (a1) of a wiring path between a terminal A and a terminal C1 and a length (b1) of a wiring path between a terminal D1 and a terminal B is substantially equal to a sum of the length (a2) of a wiring path between the terminal A and a terminal C2 and the length (b2) of a wiring path between a terminal D2 and the terminal B.

Abstract translation: 本发明的目的是提供一种包括在逆变器之间包括电路的振荡器电路的半导体器件。 在该电路中，端子A和端子C1之间的布线路径的长度（a1）和端子D1与端子B之间的布线路径的长度（b1）之和基本上等于 端子A和端子C2之间的布线路径的长度（a2）和端子D2与端子B之间的布线路径的长度（b2）。