公开(公告)号：US11139020B2

公开(公告)日：2021-10-05

申请号：US16521165

申请日：2019-07-24

Applicant: SK hynix Inc.

Inventor： Eu Joon Byun ,  Jea Young Zhang

IPC: G11C7/22 ,  G11C11/409 ,  G06F13/16 ,  G06F11/10

Abstract: A memory controller includes a mapping data controller configured to generate extended mapping data including mapping information and an additional field in response to an extended mapping data request received from a host and to generate data generation information indicating that the extended mapping data has been generated, wherein the mapping information indicates a mapping relationship between a logical block address and a physical block address and a bitmap information generator configured to receive the data generation information and generate bitmap information. The bitmap information may include information for changing a bit value corresponding to a mapping data group including the extended mapping data, among bit values included in a bitmap, to indicate the extended mapping data, and the mapping data group may include a plurality of pieces of mapping data.

公开(公告)号：US10990541B2

公开(公告)日：2021-04-27

申请号：US16522344

申请日：2019-07-25

Applicant: SK hynix Inc.

Inventor： Eu Joon Byun

IPC: G06F12/121 ,  G06F12/123 ,  G06F12/122 ,  G11C16/26 ,  G11C16/04

Abstract: A controller controls an operation of a semiconductor memory device. The controller includes a cache buffer, a request analyzer, and a cache controller. The cache buffer stores multiple cache data. The request analyzer generates request information including information on a size of read data to be read. The cache controller determines an eviction policy of the multiple cache data, based on the size of the read data in the request information.

公开(公告)号：US10990539B2

公开(公告)日：2021-04-27

申请号：US16533562

申请日：2019-08-06

Applicant: SK hynix Inc.

Inventor： Eu Joon Byun

IPC: G06F12/12 ,  G06F12/10 ,  G06F12/122

Abstract: A memory system includes a memory device and a controller. The memory device includes first and second memory groups. The controller includes a resource controller and first and second flash translation layer (FTL) cores. Each of the first and second FTL cores manages a plurality of logical addresses (LAs) that are mapped, respectively, to a plurality of physical addresses (PAs) of a corresponding memory group. The resource controller determines LA use rates of the first and second FTL cores, selects a source FTL core and a target FTL core from the first and second FTL cores using the LA use rates, and balances the LA use rates of the source FTL core and the target FTL core by moving data stored in storage spaces associated with a portion of the LAs from the source FTL core to storage spaces associated with the target FTL core.

公开(公告)号：US10970230B2

公开(公告)日：2021-04-06

申请号：US16455901

申请日：2019-06-28

Applicant: SK hynix Inc.

Inventor： Eu Joon Byun

IPC: G06F12/02 ,  G06F12/0873 ,  G06F3/06 ,  G06F12/1027

Abstract: There are provided a memory system and an operating method thereof. The memory system includes: a host for receiving and storing a host map segment; a memory device including a system block for storing map data, the memory device performing overall operations in response to an internal command; and a controller for generating the internal command for controlling the memory device in response to a host command received from the host. The controller receives the map data from the memory device and then stores the received map data, and generates the host map segment, using the map data, and then transmits the generated host map segment. A number of generatable host map segments is adjusted based on a work load calculated in a setting period.

公开(公告)号：US12242749B2

公开(公告)日：2025-03-04

申请号：US18660232

申请日：2024-05-10

Applicant: SK hynix Inc.

Inventor： Eu Joon Byun

IPC: G06F3/06 ,  G06F16/901

Abstract: Embodiments of the present disclosure relate to a memory controller and operating method thereof. According to embodiments of the present disclosure, the memory controller may generate a fused linked list which includes information of a plurality of write commands received from a host and a plurality of synchronization commands requesting a synchronization operation, and control the synchronization operation for one or more of the plurality of write commands based on the fused linked list.

公开(公告)号：US12032843B2

公开(公告)日：2024-07-09

申请号：US17157255

申请日：2021-01-25

Applicant: SK hynix Inc.

Inventor： Eu Joon Byun

IPC: G06F3/06

CPC classification number: G06F3/064 ,  G06F3/0614 ,  G06F3/0652 ,  G06F3/0659 ,  G06F3/0679

Abstract: A data processing system may include: a memory system comprising a memory device including a plurality of memory blocks; and a host suitable for dividing the memory device into a plurality of logical blocks, and including a plurality of segments each constituted by at least some of the plurality of logical blocks. The host may select a victim segment based on the number of the valid logical blocks corresponding to each of the memory blocks, and perform segment recycling on the victim segment, and one or more memory blocks may be invalidated by the segment recycling.

公开(公告)号：US11922048B2

公开(公告)日：2024-03-05

申请号：US17148116

申请日：2021-01-13

Applicant: SK hynix Inc.

Inventor： Hye Mi Kang ,  Eu Joon Byun

IPC: G06F12/00 ,  G06F3/06 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/12

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/12

Abstract: A memory controller for controlling a memory device which stores logical-to-physical (L2P) segments includes a map data storage and a map manager. The map data storage stores a plurality of physical-to-logical (P2L) segments including mapping information between a physical address of the memory device in which write data is to be stored and a logical address received from a host, in response to a write request received from the host. The map manager updates the L2P segments stored in the memory device, based on target P2L segments corresponding to a write command provided to the memory device, which have a higher priority than the other P2L segments among the plurality of P2L segments. Each of L2P segments includes mapping information between a logical address and a physical address of data stored in the memory device.

公开(公告)号：US11775214B2

公开(公告)日：2023-10-03

申请号：US17338246

申请日：2021-06-03

Applicant: SK hynix Inc.

Inventor： Hye Mi Kang ,  Eu Joon Byun

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0679

Abstract: Embodiments of the present disclosure relate to a memory system and an operating method thereof. According to the embodiments of the present disclosure, the memory system may fetch a first command from the host into a command queue, suspend execution of the first command when receiving a lock request for the first command from the host, and resume the execution of the first command when receiving an unlock request for the first command or after the first command is suspended for an amount of time corresponding to a suspend time value transmitted together with the lock request.

公开(公告)号：US11657000B2

公开(公告)日：2023-05-23

申请号：US17443727

申请日：2021-07-27

Applicant: SK hynix Inc.

Inventor： Eu Joon Byun

IPC: G06F12/00 ,  G06F12/1009 ,  G06F12/02

CPC classification number: G06F12/1009 ,  G06F12/0253 ,  G06F2212/657

Abstract: Disclosed is a memory system including: a memory device including a plurality of memory blocks; an address management component suitable for generating an address map table by sequentially mapping a logical address of write data to physical addresses of the memory blocks, in response to a write command; and a read/write control component suitable for writing the write data to a super memory block including pages of each of the memory blocks, based on the address map table, wherein the address management component maps a logical address of invalidation data which is designated by a host, to a physical address of a first memory block of the memory blocks in the address map table.

公开(公告)号：US11561725B2

公开(公告)日：2023-01-24

申请号：US17362289

申请日：2021-06-29

Applicant: SK hynix Inc.

Inventor： Hye Mi Kang ,  Eu Joon Byun

IPC: G06F3/06 ,  G06F12/0802

Abstract: Embodiments of the present disclosure relate to a system and an operating method thereof. According to embodiments of the present disclosure, a memory system may transmit a first type response indicating that first data has been cached in a cache to the host when receiving a first command requesting to write the first data from the host, and may transmit a second type response indicating success or failure of an operation of storing the first data in the memory device to the host after transmitting the first type response to the host. Further, the host may delete the first data from a write buffer after the operation of storing the first data in the memory device succeeds.