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公开(公告)号：US11300985B2
公开(公告)日：2022-04-12
申请号：US17070304
申请日：2020-10-14
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Jimmy Fort
Abstract: A device includes a current source, a first transistor connected between a first supply rail and an output terminal, and a second transistor connected between the output terminal and a first terminal of the current source, wherein a second terminal of the current source is connected to a second supply rail. A variable-gain amplifier circuit responds to a potential at the first terminal of the current source by applying a potential to the control terminal of the first transistor. A gain of the amplifier circuit is determined by a potential at the output terminal.
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公开(公告)号：US20210157392A1
公开(公告)日：2021-05-27
申请号：US17251738
申请日：2019-06-25
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Alexandre Tramoni , Jimmy Fort
IPC: G06F1/3287 , H03K3/0233
Abstract: An embodiment of the present disclosure relates to a circuit of cyclic activation of an electronic function comprising a hysteresis comparator controlling the charge of a capacitive element powering the function.
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公开(公告)号：US20210124380A1
公开(公告)日：2021-04-29
申请号：US17070304
申请日：2020-10-14
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Jimmy Fort
Abstract: A device includes a current source, a first transistor connected between a first supply rail and an output terminal, and a second transistor connected between the output terminal and a first terminal of the current source, wherein a second terminal of the current source is connected to a second supply rail. A variable-gain amplifier circuit responds to a potential at the first terminal of the current source by applying a potential to the control terminal of the first transistor. A gain of the amplifier circuit is determined by a potential at the output terminal.
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公开(公告)号：US10691840B2
公开(公告)日：2020-06-23
申请号：US15137789
申请日：2016-04-25
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Alexandre Sarafianos , Jimmy Fort , Clement Champeix , Jean-Max Dutertre , Nicolas Borrel
Abstract: A secure electronic chip including a plurality of biased semiconductor wells and a well biasing current detection circuit. Each of the wells includes a transistor and a bias contact electrically isolated from the transistor. The detection circuit is electrically coupled to each bias contact and is configured to detect a bias current passing through the bias contact that is indicative of an attempt to tamper with the electronic chip.
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公开(公告)号：US10079215B2
公开(公告)日：2018-09-18
申请号：US15789362
申请日：2017-10-20
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Alexandre Sarafianos , Mathieu Lisart , Jimmy Fort
IPC: H01L23/00 , H01L21/762 , H01L27/088
CPC classification number: H01L23/576 , H01L21/762 , H01L27/088
Abstract: An electronic chip including: a plurality of first semiconductor bars of a first conductivity type and of second semiconductor bars of a second conductivity type arranged alternately and contiguously on a region of the first conductivity type; two detection contacts arranged at the ends of each second bar; a circuit for detecting the resistance between the detection contacts of each second bar; insulating trenches extending in the second bars down to a first depth between circuit elements; and insulating walls extending across the entire width of each second bar down to a second depth greater than the first depth.
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Patent Agency Ranking
公开(公告)号：US09787171B2
公开(公告)日：2017-10-10
申请号：US14315989
申请日：2014-06-26
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Jimmy Fort
CPC classification number: H02M1/08 , G06F21/755 , Y10T307/549
Abstract: An electronic circuit includes a functional circuit in series with at least one first current source between two terminals of application of a power supply voltage. The first current source is controllable between an operating mode where it delivers a fixed current, independent from the power consumption of said functional circuit, and an operating mode where it delivers a variable current, depending on the power consumption of the functional circuit.
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37.发明申请公开(公告)号：US20170192448A1
公开(公告)日：2017-07-06
申请号：US15467927
申请日：2017-03-23
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Nicolas DEMANGE , Jimmy Fort , Thierry Soude
CPC classification number: G05F3/262 , G06F21/755 , G06K19/0723 , H01L23/576 , H03B29/00
Abstract: A method for smoothing current consumed by an electronic device is based on a series of current copying operations and on a current source delivering a reference current. The reference current is delivered in such a manner that current consumed as seen from the power supply depends on the reference current.
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38.发明授权公开(公告)号：US09678525B2
公开(公告)日：2017-06-13
申请号：US15150713
申请日：2016-05-10
Applicant: STMICROELECTRONICS (ROUSSET) SAS
Inventor： Nicolas Demange , Jimmy Fort , Thierry Soude
CPC classification number: G05F3/262 , G06F21/755 , G06K19/0723 , H01L23/576 , H03B29/00
Abstract: A method for smoothing current consumed by an electronic device is based on a series of current copying operations and on a current source delivering a reference current. The reference current is delivered in such a manner that current consumed as seen from the power supply depends on the reference current.
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公开(公告)号：US09190969B2
公开(公告)日：2015-11-17
申请号：US13827044
申请日：2013-03-14
Applicant: STMICROELECTRONICS (Rousset) SAS
Inventor： Jimmy Fort , Thierry Soude
CPC classification number: G05F1/575 , H03F3/45179
Abstract: The regulator with a low dropout voltage comprises an error amplifier comprising a differential pair of input transistors and a circuit with folded cascode structure connected to the output of the said differential pair, an output stage connected to the output node of the error amplifier, and a Miller compensation capacitor connected between the output stage and the cascode node on the output side (XP) of the cascode circuit; the error amplifier furthermore comprises at least one inverting amplifier module in a feedback loop between the said cascode node and the gate of the cascode transistor of the cascode circuit connected between the said cascode node and the said output node.
Abstract translation: 具有低压降电压的调节器包括误差放大器，该误差放大器包括差分输入晶体管对和连接到所述差分对的输出的折叠共源共栅结构的电路，连接到误差放大器的输出节点的输出级，以及 米勒补偿电容连接在共源共栅电路的输出侧（XP）的输出级与共源共栅节点之间; 误差放大器还包括在所述共源共栅节点和连接在所述共源共栅节点和所述输出节点之间的共源共栅电路的共源共栅晶体管的栅极之间的反馈回路中的至少一个反相放大器模块。
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40.发明申请Device for Generating an Adjustable Bandgap Reference Voltage with Large Power Supply Rejection Rate 审中-公开用于产生具有大电源抑制率的可调带隙参考电压的装置公开(公告)号：US20150153753A1
公开(公告)日：2015-06-04
申请号：US14616481
申请日：2015-02-06
Applicant: STMICROELECTRONICS (ROUSSET) SAS
Inventor： Jimmy Fort , Thierry Soude
IPC: G05F1/625
Abstract: An adjustable bandgap reference voltage includes a first circuit for generating IPTAT, a second circuit for generating ICTAT, and an output module configured to generate the reference voltage. The first circuit includes a first amplifier connected to terminals of a core for equalizing voltages across the terminals, where the first amplifier has a first stage that is biased by the current inversely proportional to absolute temperature and is arranged according to a folded setup with first PMOS transistors arranged according to a common-gate setup. The first circuit also includes a feedback stage with an input connected to the first amplifier output. The feedback stage output is connected to the first stage input and to a terminal of the core. The second circuit includes a follower amplifier connected to a terminal of the core and separated from the first amplifier and the output module is connected to the feedback stage.
Abstract translation: 可调节带隙参考电压包括用于产生IPTAT的第一电路，用于产生ICTAT的第二电路和被配置为产生参考电压的输出模块。 第一电路包括连接到芯的端子的第一放大器，用于均衡端子两端的电压，其中第一放大器具有被绝对温度成反比的电流偏置的第一级，并且根据折叠设置与第一PMOS 根据共门设置布置的晶体管。 第一电路还包括具有连接到第一放大器输出的输入的反馈级。 反馈级输出连接到第一级输入端和核心端子。 第二电路包括连接到芯的端子并与第一放大器分离的跟随放大器，并且输出模块连接到反馈级。
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