公开(公告)号：US20240105268A1

公开(公告)日：2024-03-28

申请号：US18529897

申请日：2023-12-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungyeon Kim ,  Daeseok Byeon ,  Pansuk Kwak ,  Hongsoo Jeon

IPC: G11C16/24 ,  G11C5/06 ,  G11C16/26 ,  H10B41/27 ,  H10B43/27

CPC classification number: G11C16/24 ,  G11C5/06 ,  G11C16/26 ,  H10B41/27 ,  H10B43/27

Abstract: A memory device includes: a memory cell array including a first memory block and a second memory block adjacently disposed in a first direction, driving signal lines respectively corresponding to vertically stacked word lines, and a pass transistor circuit including an odd number of pass transistor groups and connected between the driving signal lines and the memory cell array. One of the odd number of pass transistor groups includes a first pass transistor connected between a first word line of the first memory block and a first driving signal line among the driving signal lines, and a second pass transistor connected between a first word line of the second memory block and the first driving signal line adjacently disposed to the first pass transistor in a second direction.

公开(公告)号：US11901001B2

公开(公告)日：2024-02-13

申请号：US17569786

申请日：2022-01-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jooyong Park ,  Pansuk Kwak ,  Daeseok Byeon

IPC: G11C7/24 ,  G11C16/10 ,  G11C13/00 ,  G11C5/06

CPC classification number: G11C13/0059 ,  G11C5/063 ,  G11C13/004 ,  G11C13/0028 ,  G11C13/0038 ,  G11C13/0069

Abstract: Provided are memory devices and memory systems. The memory device includes a memory cell array in a first semiconductor layer and including word lines stacked in a first direction, and channel structures passing through the word lines in the first direction; a control logic circuit in a second semiconductor layer located below the first semiconductor layer in the first direction; and a physical unclonable function (PUF) circuit including a plurality of through electrodes passing through the first semiconductor layer and the second semiconductor layer, and configured to generate PUF data according to resistance values of the plurality of through electrodes, and generate the PUF data based on a node voltage between through electrodes connected in series, among the plurality of through electrodes.

公开(公告)号：US20230317655A1

公开(公告)日：2023-10-05

申请号：US18328359

申请日：2023-06-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jooyong PARK ,  Chanho Kim ,  Pansuk Kwak ,  Daeseok Byeon

IPC: H01L23/00 ,  H01L21/66 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00

CPC classification number: H01L24/08 ,  H01L22/20 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/80908 ,  H01L2225/06596 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A memory device includes a memory chip including a memory cell array connected to first word lines and first bit lines, first word line bonding pads respectively connected to the first word lines, and first bit line bonding pads respectively connected to the first bit lines, and a peripheral circuit chip, wherein the peripheral circuit chip includes a test cell array connected to second word lines and second bit lines, second word line bonding pads respectively connected to the first word line bonding pads, second bit line bonding pads respectively connected to the first bit line bonding pads, and a peripheral circuit connected to the second word line bonding pads and the second word lines or the second bit line bonding pads and the second bit lines.

公开(公告)号：US11721655B2

公开(公告)日：2023-08-08

申请号：US17381782

申请日：2021-07-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jooyong Park ,  Chanho Kim ,  Pansuk Kwak ,  Daeseok Byeon

IPC: H01L25/065 ,  H01L23/00 ,  H01L21/66 ,  H01L25/18 ,  H01L25/00

CPC classification number: H01L24/08 ,  H01L22/20 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/80908 ,  H01L2225/06596 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A memory device includes a memory chip including a memory cell array connected to first word lines and first bit lines, first word line bonding pads respectively connected to the first word lines, and first bit line bonding pads respectively connected to the first bit lines, and a peripheral circuit chip, wherein the peripheral circuit chip includes a test cell array connected to second word lines and second bit lines, second word line bonding pads respectively connected to the first word line bonding pads, second bit line bonding pads respectively connected to the first bit line bonding pads, and a peripheral circuit connected to the second word line bonding pads and the second word lines or the second bit line bonding pads and the second bit lines.

公开(公告)号：US11462275B2

公开(公告)日：2022-10-04

申请号：US17227501

申请日：2021-04-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungyeon Kim ,  Daeseok Byeon ,  Pansuk Kwak ,  Hongsoo Jeon

IPC: G11C16/24 ,  G11C5/06 ,  G11C16/26 ,  H01L27/11556 ,  H01L27/11582

Abstract: A memory device includes; a memory cell array including a first memory block and a second memory block adjacently disposed in a first direction, driving signal lines respectively corresponding to vertically stacked word lines, and a pass transistor circuit including an odd number of pass transistor groups and connected between the driving signal lines and the memory cell array. One of the odd number of pass transistor groups includes a first pass transistor connected between a first word line of the first memory block and a first driving signal line among the driving signal lines, and a second pass transistor connected between a first word line of the second memory block and the first driving signal line adjacently disposed to the first pass transistor in a second direction.

公开(公告)号：US20220277792A1

公开(公告)日：2022-09-01

申请号：US17746393

申请日：2022-05-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyunghwa Yun ,  Chanho Kim ,  Pansuk Kwak

IPC: G11C16/08 ,  G11C16/10 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11573

Abstract: A memory device including: a memory cell array disposed in a first semiconductor layer, the memory cell array including a plurality of wordlines extended in a first direction and stacked in a second direction substantially perpendicular to the first direction; and a plurality of pass transistors disposed in the first semiconductor layer, wherein a first pass transistor of the plurality of pass transistors is disposed between a first signal line of a plurality of signal lines and a first wordline of the plurality of wordlines, and wherein the plurality of signal lines are arranged at the same level as a common source line.

公开(公告)号：US10763278B2

公开(公告)日：2020-09-01

申请号：US16243837

申请日：2019-01-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyunghwa Yun ,  Pansuk Kwak ,  Chanho Kim ,  Junghwa Lee

IPC: H01L27/11582 ,  H01L23/528 ,  H01L23/535 ,  H01L27/11573

Abstract: A semiconductor memory device includes a substrate having a cell array region and a contact region, a stack structure including a plurality of gate electrodes on the cell array region and the contact region, a plurality of cell vertical channel structures extending through the stack structure on the cell array region, and a contact structure disposed beside of the stack structure on a top surface of the substrate and disposed along a line extending from the cell array region toward the contact region. The height of the contact structure on the cell array region is different from the height of the contact structure on the contact region.