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31.发明申请Methods and Apparatus for Scalable Array Processor Interrupt Detection and Response 失效用于可扩展阵列处理器中断检测和响应的方法和装置公开(公告)号：US20120173849A1
公开(公告)日：2012-07-05
申请号：US13417490
申请日：2012-03-12
CPC分类号： G06F9/3865 , G06F9/30058 , G06F9/3861 , G06F9/4812 , G06F11/27 , G06F13/26 , Y02D10/14 , Y02D10/24
摘要： Hardware and software techniques for interrupt detection and response in a scalable pipelined array processor environment are described. Utilizing these techniques, a sequential program execution model with interrupts can be maintained in a highly parallel scalable pipelined array processing containing multiple processing elements and distributed memories and register files. When an interrupt occurs, interface signals are provided to all PEs to support independent interrupt operations in each PE dependent upon the local PE instruction sequence prior to the interrupt. Processing/element exception interrupts are supported and low latency interrupt processing is also provided for embedded systems where real time signal processing is to required. Further, a hierarchical interrupt structure is used allowing a generalized debug approach using debut interrupts and a dynamic debut monitor mechanism.
摘要翻译： 描述了可扩展流水线阵列处理器环境中的中断检测和响应的硬件和软件技术。 利用这些技术，可以在包含多个处理元件和分布式存储器和寄存器文件的高度并行的可扩展流水线阵列处理中维持具有中断的顺序程序执行模型。 当发生中断时，接口信号提供给所有PE，以支持每个PE中的独立中断操作，取决于中断前的本地PE指令序列。 支持处理/元素异常中断，并为需要实时信号处理的嵌入式系统提供低延迟中断处理。 此外，使用分层中断结构，允许使用初次中断的通用调试方法和动态登场监视机制。
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32.发明申请公开(公告)号：US20120124335A1
公开(公告)日：2012-05-17
申请号：US13344339
申请日：2012-01-05
申请人： Gerald G. Pechanek , David Carl Strube , Edwin Franklin Barry , Charles W. Kurak, JR. , Carl Donald Busboom , Dale Edward Schneider , Nikos P. Pitsianis , Grayson Morris , Edward A. Wolff , Patrick R. Marchand , Ricardo E. Rodriguez , Marco C. Jacobs
发明人： Gerald G. Pechanek , David Carl Strube , Edwin Franklin Barry , Charles W. Kurak, JR. , Carl Donald Busboom , Dale Edward Schneider , Nikos P. Pitsianis , Grayson Morris , Edward A. Wolff , Patrick R. Marchand , Ricardo E. Rodriguez , Marco C. Jacobs
IPC分类号： G06F9/312
CPC分类号： G06F15/82 , G06F9/30145 , G06F11/263 , Y10S707/99943
摘要： Details of a highly cost effective and efficient implementation of a manifold array (ManArray) architecture and instruction syntax for use therewith are described herein. Various aspects of this approach include the regularity of the syntax, the relative ease with which the instruction set can be represented in database form, the ready ability with which tools can be created, the ready generation of self-checking codes and parameterized test cases. Parameterizations can be fairly easily mapped and system maintenance is significantly simplified.
摘要翻译： 这里描述了使用歧管阵列（ManArray）架构和指令语法的高成本有效和高效的实现的细节。 该方法的各个方面包括语法的规律性，指示集可以以数据库形式表示的相对容易程度，可以创建工具的就绪能力，即时生成自检代码和参数化测试用例。 可以很容易地映射参数化，并显着简化系统维护。
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33.发明授权Methods and apparatus for scalable array processor interrupt detection and response 有权用于可扩展阵列处理器中断检测和响应的方法和装置公开(公告)号：US08161267B2
公开(公告)日：2012-04-17
申请号：US12956316
申请日：2010-11-30
CPC分类号： G06F9/3865 , G06F9/30058 , G06F9/3861 , G06F9/4812 , G06F11/27 , G06F13/26 , Y02D10/14 , Y02D10/24
摘要： Hardware and software techniques for interrupt detection and response in a scalable pipelined array processor environment are described. Utilizing these techniques, a sequential program execution model with interrupts can be maintained in a highly parallel scalable pipelined array processing containing multiple processing elements and distributed memories and register files. When an interrupt occurs, interface signals are provided to all PEs to support independent interrupt operations in each PE dependent upon the local PE instruction sequence prior to the interrupt. Processing/element exception interrupts are supported and low latency interrupt processing is also provided for embedded systems where real time signal processing is required. Further, a hierarchical interrupt structure is used allowing a generalized debug approach using debut interrupts and a dynamic debut monitor mechanism.
摘要翻译： 描述了可扩展流水线阵列处理器环境中的中断检测和响应的硬件和软件技术。 利用这些技术，可以在包含多个处理元件和分布式存储器和寄存器文件的高度并行的可扩展流水线阵列处理中维持具有中断的顺序程序执行模型。 当发生中断时，接口信号提供给所有PE，以支持每个PE中的独立中断操作，取决于中断前的本地PE指令序列。 支持处理/元件异常中断，并为需要实时信号处理的嵌入式系统提供低延迟中断处理。 此外，使用分层中断结构，允许使用初次中断的通用调试方法和动态登场监视机制。
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34.发明授权公开(公告)号：US07962667B2
公开(公告)日：2011-06-14
申请号：US11827548
申请日：2007-07-12
申请人： Gerald G. Pechanek , David Carl Strube , Edwin Frank Barry , Charles W. Kurak, Jr. , Carl Donald Busboom , Dale Edward Schneider , Nikos P. Pitsianis , Grayson Morris , Edward A. Wolff , Patrick R. Marchand , Ricardo E. Rodriguez , Marco C. Jacobs
发明人： Gerald G. Pechanek , David Carl Strube , Edwin Frank Barry , Charles W. Kurak, Jr. , Carl Donald Busboom , Dale Edward Schneider , Nikos P. Pitsianis , Grayson Morris , Edward A. Wolff , Patrick R. Marchand , Ricardo E. Rodriguez , Marco C. Jacobs
CPC分类号： G06F15/82 , G06F9/30145 , G06F11/263 , Y10S707/99943
摘要： Details of a highly cost effective and efficient implementation of a manifold array (ManArray) architecture and instruction syntax for use therewith are described herein. Various aspects of this approach include the regularity of the syntax, the relative ease with which the instruction set can be represented in database form, the ready ability with which tools can be created, the ready generation of self-checking codes and parameterized test cases. Parameterizations can be fairly easily mapped and system maintenance is significantly simplified.
摘要翻译： 这里描述了使用歧管阵列（ManArray）架构和指令语法的高成本有效和高效的实现的细节。 该方法的各个方面包括语法的规律性，指示集可以以数据库形式表示的相对容易程度，可以创建工具的就绪能力，即时生成自检代码和参数化测试用例。 可以很容易地映射参数化，并显着简化系统维护。
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35.发明授权Methods and apparatus for adapting pipeline stage latency based on instruction type 有权基于指令类型调整流水线级延迟的方法和装置公开(公告)号：US07809932B1
公开(公告)日：2010-10-05
申请号：US10805803
申请日：2004-03-22
CPC分类号： G06F9/30079 , G06F9/30145 , G06F9/3869 , G06F9/3885
摘要： Processor pipeline controlling techniques are described which take advantage of the variation in critical path lengths of different instructions to achieve increased performance. By examining a processor's instruction set and execution unit implementation's critical timing paths, instructions are classified into speed classes. Based on these speed classes, one pipeline is presented where hold signals are used to dynamically control the pipeline based on the instruction class in execution. An alternative pipeline supporting multiple classes of instructions is presented where the pipeline clocking is dynamically changed as a result of decoded instruction class signals. A single pass synthesis methodology for multi-class execution stage logic is also described. For dynamic class variable pipeline processors, the mix of instructions can have a great effect on processor performance and power utilization since both can vary by the program mix of instruction classes. Application code can be given new degrees of optimization freedom where instruction class and the mix of instructions can be chosen based on performance and power requirements.
摘要翻译： 描述了处理器流水线控制技术，其利用不同指令的关键路径长度的变化来实现增加的性能。 通过检查处理器的指令集和执行单元实现的关键时序路径，指令被分为速度等级。 基于这些速度等级，提出了一个管道，其中使用保持信号来基于执行中的指令类来动态地控制流水线。 提出了支持多类指令的替代流水线，其中流水线时钟作为解码指令类信号的结果动态地改变。 还描述了用于多类执行级逻辑的单程合成方法。 对于动态类变量流水线处理器，指令的混合可以对处理器性能和功率利用率产生很大的影响，因为它们可以根据指令类的程序组合而变化。 应用代码可以给出新的优化自由度，其中可以基于性能和功率要求来选择指令类和指令混合。
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公开(公告)号：US07565490B1
公开(公告)日：2009-07-21
申请号：US11313587
申请日：2005-12-20
IPC分类号： G06F12/00
CPC分类号： G06F12/0875 , G06T1/00 , G06T15/005 , G06T15/04 , G06T2200/28
摘要： Circuits, methods, and apparatus that provide an L2 cache that services requests out of order. This L2 cache processes requests that are hits without waiting for data corresponding to requests that are misses to be returned from a graphics memory. A first auxiliary memory, referred to as a side pool, is used for holding subsequent requests for data at a specific address while a previous request for data at that address is serviced by a frame buffer interface and graphics memory. This L2 cache may also use a second auxiliary memory, referred to as a take pool, to store requests or pointers to data that is ready to be retrieved from an L2 cache.
摘要翻译： 提供二级缓存的电路，方法和设备，以使服务请求无序。 该L2缓存处理作为命中的请求，而不等待与从图形存储器返回的未命中的请求对应的数据。 称为侧池的第一辅助存储器用于在特定地址处保留对数据的后续请求，同时由该缓冲区接口和图形存储器为该地址提供先前的数据请求。 该L2高速缓存还可以使用称为采取池的第二辅助存储器来存储对准备从L2高速缓存检索的数据的请求或指针。
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37.发明授权公开(公告)号：US06735690B1
公开(公告)日：2004-05-11
申请号：US09598566
申请日：2000-06-21
IPC分类号： G06F1500
CPC分类号： G06F9/30054 , G06F9/30101 , G06F9/30112 , G06F9/325
摘要： A processor with a generalized eventpoint architecture, which is scalable for use in a very long instruction word (VLIW) array processor, such as the manifold array (ManArray) processor is described. In one aspect, generalized processor event (p-event) detection facilities are provided by use of compares to check if an instruction address, a data memory address, an instruction, a data value, arithmetic-condition flags, or other processor change of state eventpoint has occurred. In another aspect, generalized processor action (p-action) facilities are provided to cause a change in the program flow by loading the program counter with a new instruction address, generate an interrupt, signal a semaphore, log or count the p-event, time stamp the event, initiate a background operation, or to cause other p-actions to occur. The generalized facilities are defined in the eventpoint architecture as consisting of a control register and three eventpoint parameters, namely at least one register to compare against, a register containing a second compare register, a vector address, or parameter to be passed, and a count or mask register. Based upon this generalized eventpoint architecture, new capabilities are enabled. For example, auto-looping with capabilities to branch out of a nested auto-loop upon detection of a specified condition, background DMA facilities, the ability to link a chain of p-events together for debug purposes, and others are all important capabilities which are readily obtained.
摘要翻译： 描述了具有广泛事件点架构的处理器，其可扩展以用于非常长的指令字（VLIW）阵列处理器，例如歧管阵列（ManArray）处理器。 在一个方面，通过使用比较来提供广义处理器事件（p事件）检测设施，以检查指令地址，数据存储器地址，指令，数据值，算术条件标志或其他处理器状态变化 事件点已发生。 在另一方面，提供通用处理器动作（p-action）功能以通过用新的指令地址加载程序计数器来产生程序流程的改变，生成中断，信号信号，记录或计数p事件， 事件时间戳，启动后台操作，或导致其他动作发生。 广义设施在事件点架构中被定义为由控制寄存器和三个事件点参数组成，即至少要有一个要比较的寄存器，一个包含第二个比较寄存器的寄存器，一个向量地址或要传递的参数，以及一个计数 或屏蔽寄存器。 基于这种广义的事件点架构，启用了新的功能。 例如，在检测到指定的条件时，自动循环具有分支出嵌套自动循环的功能，后台DMA设施，将p个事件链链接在一起用于调试目的的能力等等都是重要的功能 容易获得。
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公开(公告)号：US08963940B1
公开(公告)日：2015-02-24
申请号：US11695557
申请日：2007-04-02
CPC分类号： G09G5/395 , G09G2360/08 , G09G2370/022 , G09G2370/10
摘要： One embodiment of the invention sets forth a method for transmitting display data to a display device. The method includes the steps of receiving a contract for a frame of display data, preparing the frame of display data to ensure the timing requirements of the display device can be satisfied based on the contract, and transmitting the frame of display data to the display device while the contract is pending.
摘要翻译： 本发明的一个实施例提出了一种将显示数据发送到显示装置的方法。 该方法包括以下步骤：接收一帧显示数据的合同，准备显示数据的帧，以确保基于合约可以满足显示设备的定时要求，并将显示数据的帧发送到显示设备 而合同正在等待。
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39.发明申请Methods and Apparatus for Scalable Array Processor Interrupt Detection and Response 失效用于可扩展阵列处理器中断检测和响应的方法和装置公开(公告)号：US20130283012A1
公开(公告)日：2013-10-24
申请号：US13916877
申请日：2013-06-13
IPC分类号： G06F9/30
CPC分类号： G06F9/3865 , G06F9/30058 , G06F9/3861 , G06F9/4812 , G06F11/27 , G06F13/26 , Y02D10/14 , Y02D10/24
摘要： Hardware and software techniques for interrupt detection and response in a scalable pipelined array processor environment are described. Utilizing these techniques, a sequential program execution model with interrupts can be maintained in a highly parallel scalable pipelined array processing containing multiple processing elements and distributed memories and register files. When an interrupt occurs, interface signals are provided to all PEs to support independent interrupt operations in each PE dependent upon the local PE instruction sequence prior to the interrupt. Processing/element exception interrupts are supported and low latency interrupt processing is also provided for embedded systems where real time signal processing is required. Further, a hierarchical interrupt structure is used allowing a generalized debug approach using debut interrupts and a dynamic debut monitor mechanism.
摘要翻译： 描述了可扩展流水线阵列处理器环境中的中断检测和响应的硬件和软件技术。 利用这些技术，可以在包含多个处理元件和分布式存储器和寄存器文件的高度并行的可扩展流水线阵列处理中维持具有中断的顺序程序执行模型。 当发生中断时，接口信号提供给所有PE，以支持每个PE中的独立中断操作，取决于中断前的本地PE指令序列。 支持处理/元件异常中断，并为需要实时信号处理的嵌入式系统提供低延迟中断处理。 此外，使用分层中断结构，允许使用初次中断的通用调试方法和动态登场监视机制。
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40.发明授权Methods and apparatus for adapting pipeline stage latency based on instruction type 有权基于指令类型调整流水线级延迟的方法和装置公开(公告)号：US08413086B2
公开(公告)日：2013-04-02
申请号：US12861896
申请日：2010-08-24
IPC分类号： G06F17/50
CPC分类号： G06F9/30079 , G06F9/30145 , G06F9/3869 , G06F9/3885
摘要： Processor pipeline controlling techniques are described which take advantage of the variation in critical path lengths of different instructions to achieve increased performance. By examining a processor's instruction set and execution unit implementation's critical timing paths, instructions are classified into speed classes. Based on these speed classes, one pipeline is presented where hold signals are used to dynamically control the pipeline based on the instruction class in execution. An alternative pipeline supporting multiple classes of instructions is presented where the pipeline clocking is dynamically changed as a result of decoded instruction class signals. A single pass synthesis methodology for multi-class execution stage logic is also described. For dynamic class variable pipeline processors, the mix of instructions can have a great effect on processor performance and power utilization since both can vary by the program mix of instruction classes. Application code can be given new degrees of optimization freedom where instruction class and the mix of instructions can be chosen based on performance and power requirements.
摘要翻译： 描述了处理器流水线控制技术，其利用不同指令的关键路径长度的变化来实现增加的性能。 通过检查处理器的指令集和执行单元实现的关键时序路径，指令被分为速度等级。 基于这些速度等级，提出了一个管道，其中使用保持信号来基于执行中的指令类来动态地控制流水线。 提出了支持多类指令的替代流水线，其中流水线时钟作为解码指令类信号的结果动态地改变。 还描述了用于多类执行级逻辑的单程合成方法。 对于动态类变量流水线处理器，指令的混合可以对处理器性能和功率利用率产生很大的影响，因为它们可以根据指令类的程序组合而变化。 应用代码可以给出新的优化自由度，其中可以基于性能和功率要求来选择指令类和指令混合。
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