公开(公告)号：US06236596B1

公开(公告)日：2001-05-22

申请号：US09461376

申请日：1999-12-15

Applicant: Daniel Sobek ,  Timothy James Thurgate ,  Scott D. Luning ,  Vei-Han Chan ,  Sameer S. Haddad

Inventor： Daniel Sobek ,  Timothy James Thurgate ,  Scott D. Luning ,  Vei-Han Chan ,  Sameer S. Haddad

IPC: G11C1134

CPC classification number: G11C16/14

Abstract: A method and apparatus for reducing band-to-band currents during the erasure of a flash EEPROM memory cell is provided. The apparatus has a back biasing connection on the substrate at which a biasing voltage is applied during erasure of the flash EEPROM memory cell. The method of applying the biasing voltage to the back biasing connection during erasure of the flash EEPROM memory cell reduces band-to-band current between the source region and the substrate during erasure of the flash memory cell. This reduction provides for gate size reduction in flash memory cells without inducing detrimental short channel effects.

Abstract translation: 提供了一种用于在快速EEPROM存储单元的擦除期间减小带 - 带电流的方法和装置。 该装置在衬底上具有背偏压连接，在擦除EEPROM存储单元期间施加偏置电压。 在闪存EEPROM存储单元擦除期间将偏置电压施加到反向偏置连接的方法在擦除闪速存储单元期间减少源区和衬底之间的带间电流。 这种减少提供了闪存单元的栅极尺寸减小，而不会引起有害的短沟道效应。

公开(公告)号：US6051882A

公开(公告)日：2000-04-18

申请号：US905974

申请日：1997-08-05

Applicant: Steven Avanzino ,  Subhash Gupta ,  Rich Klein ,  Scott D. Luning ,  Ming-Rin Lin

Inventor： Steven Avanzino ,  Subhash Gupta ,  Rich Klein ,  Scott D. Luning ,  Ming-Rin Lin

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/52

CPC classification number: H01L23/5226 ,  H01L21/76807 ,  H01L21/76813 ,  H01L21/76877 ,  H01L21/76885 ,  H01L2924/0002

Abstract: A method of fabricating an interconnection level of conductive lines and connecting vias separated by insulation for integrated circuits and substrate carriers for semiconductor devices using a reverse damascene in the formation of the conductive lines and vias. A conductive line pattern is first used to etch completely through the layer to form conductive line openings. The openings are completely filled with a conductive material and planarized so that the surfaces of the conductive material and the insulating layer are coplanar. A via pattern is aligned perpendicular to the conductive lines and the conductive material is etched half way through the conductive lines in other than the areas covered by the via pattern. The openings thus created in the upper portion of the conductive lines are filled with insulating material to complete the dual damascene interconnection level with the conductive lines in the lower portion of the insulating layer and upwardly projecting vias in the upper portion of the layer. In addition, a triple damascene layer is formed by starting with an insulating layer about one-third thicker than normal and by combining the standard dual damascene method with the above described method. The resulting interconnection level structure comprises conductive lines having upwardly and downwardly projecting vias.

Abstract translation: 一种制造导线的互连电平的方法，以及用于集成电路的绝缘和用于半导体器件的衬底载体分离的通孔的方法，其使用反向镶嵌来形成导电线和通孔。 首先使用导电线图案来完全蚀刻该层以形成导电线开口。 开口完全被导电材料填充并平坦化，使得导电材料和绝缘层的表面是共面的。 通孔图案垂直于导电线对齐，并且导电材料被除了通孔图案覆盖的区域之外的一半蚀刻通过导电线。 由此在导电线的上部形成的开口用绝缘材料填充，以完成与绝缘层下部的导电线和层的上部向上突出的通孔的双镶嵌互连水平。 此外，通过从绝对层开始比正常厚约三分之一的厚度并通过将标准双镶嵌方法与上述方法组合来形成三镶嵌层。 所产生的互连级联结构包括具有向上和向下突出的通孔的导线。

公开(公告)号：US5888867A

公开(公告)日：1999-03-30

申请号：US23241

申请日：1998-02-13

Applicant: Janet Wang ,  Scott D. Luning ,  Vei-Han Chan ,  Nicholas H. Tripsas

Inventor： Janet Wang ,  Scott D. Luning ,  Vei-Han Chan ,  Nicholas H. Tripsas

IPC: H01L21/28 ,  H01L21/3215 ,  H01L21/336 ,  H01L29/423 ,  H01L29/49 ,  H01L21/8247

CPC classification number: H01L29/66825 ,  H01L21/2807 ,  H01L21/28105 ,  H01L21/32155 ,  H01L29/42324 ,  H01L29/4966

Abstract: Aspects for forming a Flash EPROM cell with an adjustable threshold voltage are described. In a method aspect, the method includes forming a substrate structure to establish a foundation for cell formation, and forming a gate structure with a floating gate layer comprising polysilicon-germanium (poly-SiGe) of a non-uniform Ge concentration on the substrate structure. The method further includes forming source and drain regions within the substrate structure, the drain region having a different threshold voltage than the source region. In a further aspect, a Flash EPROM cell with an adjustable threshold voltage includes a substrate structure as a foundation for the cell. The cell further includes a gate structure on the substrate structure, the gate structure comprising a floating gate layer of polysilicon-germanium (poly-SiGe) of non-uniform Ge concentration. Additionally, source and drain regions are included in the substrate structure bordering the gate structure, the drain region having a differing threshold voltage than the source region.

Abstract translation: 描述了形成具有可调阈值电压的闪存EPROM单元的方面。 在方法方面，该方法包括形成衬底结构以建立细胞形成的基础，以及在衬底结构上形成具有包含不均匀Ge浓度的多晶锗（多晶硅）的浮栅的栅极结构 。 该方法还包括在衬底结构内形成源极和漏极区域，漏极区域具有与源极区域不同的阈值电压。 在另一方面，具有可调阈值电压的闪存EPROM单元包括作为单元的基础的衬底结构。 电池还包括在衬底结构上的栅极结构，栅极结构包括具有不均匀Ge浓度的多晶硅 - 锗（多晶SiGe）的浮栅。 此外，源极和漏极区域包括在与栅极结构接壤的衬底结构中，漏极区域具有与源极区域不同的阈值电压。

公开(公告)号：US5686354A

公开(公告)日：1997-11-11

申请号：US478324

申请日：1995-06-07

Applicant: Steven Avanzino ,  Subhash Gupta ,  Rich Klein ,  Scott D. Luning ,  Ming-Ren Lin

Inventor： Steven Avanzino ,  Subhash Gupta ,  Rich Klein ,  Scott D. Luning ,  Ming-Ren Lin

IPC: H01L21/768 ,  H01L21/28

CPC classification number: H01L21/76831 ,  H01L21/76807

Abstract: A dual damascene method of fabricating an interconnection level of conductive lines and connecting vias separated by insulation for integrated circuits and substrate carriers for semiconductor devices using a thin protective via mask to form the via openings. A conductive line mask pattern is used to form conductive line openings in an insulating layer. Next, a thin protective layer of conformal material is deposited in the conducive line opening. The protective layer and the insulating layer each have etch resistance to others etchant. Using a via mask pattern, openings are etching the protective layer with the insulating layer serving as and etch stop. Next via openings are etched in the insulating material using the openings in the thin protective layer as the etch mask. If the protective layer is a conductive material, it is removed from the surface of the insulating layer either before or after the conductive line and via openings are filled with a conductive material. If the protective material is an insulating material, it is entirely removed before filling the conductive line and via openings conductive material.

Abstract translation: 一种双镶嵌方法，用于制造导线的互连级别并且连接用于集成电路的绝缘和用于半导体器件的衬底载体的通孔，其使用薄的保护性通孔掩模形成通孔。 导电线掩模图案用于在绝缘层中形成导电线路开口。 接下来，在导电线路开口中沉积有保形材料的薄保护层。 保护层和绝缘层各自具有对其它蚀刻剂的耐蚀刻性。 使用通孔掩模图案，开口蚀刻保护层，绝缘层用作蚀刻停止。 接下来通过开口被蚀刻在绝缘材料中，使用薄保护层中的开口作为蚀刻掩模。 如果保护层是导电材料，则在导电线之前或之后将其从绝缘层的表面去除，并且通孔开口填充有导电材料。 如果保护材料是绝缘材料，则在填充导电线和通孔开口导电材料之前将其完全去除。

公开(公告)号：US20090267152A1

公开(公告)日：2009-10-29

申请号：US12496133

申请日：2009-07-01

Applicant: Paul R. Besser ,  Scott D. Luning

Inventor： Paul R. Besser ,  Scott D. Luning

IPC: H01L29/786 ,  H01L21/336

CPC classification number: H01L29/66628 ,  H01L29/66772

Abstract: A semiconductor device is disclosed having a conductive gate structure overlying a semiconductor layer having a major surface. An isolation material is recessed within a trench region below the major surface of the semiconductor layer. An epitaxial layer is formed overlying a portion of the major surface and on an active region forming a sidewall of the trench.

Abstract translation: 公开了一种半导体器件，其具有覆盖具有主表面的半导体层的导电栅极结构。 隔离材料凹陷在半导体层的主表面下方的沟槽区域内。 形成外延层，覆盖主表面的一部分和形成沟槽侧壁的有源区。

公开(公告)号：US06787464B1

公开(公告)日：2004-09-07

申请号：US10189048

申请日：2002-07-02

Applicant: Jon D. Cheek ,  Scott D. Luning

Inventor： Jon D. Cheek ,  Scott D. Luning

IPC: H01L2144

CPC classification number: H01L29/665 ,  H01L21/28518 ,  H01L21/823418 ,  H01L21/823443 ,  H01L21/823456 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/82385 ,  H01L29/7833

Abstract: The present invention is generally directed to various methods of forming metal silicide regions on transistors based upon gate critical dimensions. In one illustrative embodiment, the method comprises forming a layer of refractory metal above a plurality of transistors, reducing a thickness of at least a portion of the layer of refractory metal above at least some of the transistors and performing at least one anneal process to form metal silicide regions above the transistors. In another illustrative embodiment, the method comprises forming a layer of refractory metal above the plurality of transistors, reducing the thickness of the layer of refractory metal above a first of the transistors having a gate electrode with a critical dimension that is less than a critical dimension of a gate electrode structure of another of the plurality of transistors, and performing at least one anneal process to form metal silicide regions on the plurality of transistors. In yet another illustrative embodiment, the method comprises forming a layer of refractory metal to an original thickness above a plurality of transistors, reducing the original thickness of a portion of the layer of refractory metal above at least some of the transistors to define a layer of refractory metal having multiple thicknesses, and performing at least one anneal process to convert portions of the layer of refractory metal having multiple thicknesses to metal silicide regions on the transistors.

Abstract translation: 本发明一般涉及基于栅极临界尺寸在晶体管上形成金属硅化物区域的各种方法。 在一个说明性实施例中，该方法包括在多个晶体管上形成难熔金属层，减少至少部分晶体管的至少一部分难熔金属的厚度，并执行至少一个退火工艺以形成 晶体管上方的金属硅化物区域。 在另一示例性实施例中，该方法包括在多个晶体管上方形成难熔金属层，减小了具有栅极电极的第一晶体管之上的难熔金属层的厚度，临界尺寸小于临界尺寸 的多个晶体管中的另一个晶体管的栅极电极结构，并且执行至少一个退火工艺以在所述多个晶体管上形成金属硅化物区域。 在另一个说明性实施例中，该方法包括在多个晶体管上方形成原始厚度的难熔金属层，将难熔金属层的一部分的一部分的原始厚度减小到至少一些晶体管之上以限定一层 具有多个厚度的难熔金属，并且执行至少一个退火工艺以将具有多个厚度的难熔金属层的部分转换成晶体管上的金属硅化物区域。

公开(公告)号：US06624035B1

公开(公告)日：2003-09-23

申请号：US09523631

申请日：2000-03-13

Applicant: Scott D. Luning ,  David Donggang Wu ,  Massud Aminpur

Inventor： Scott D. Luning ,  David Donggang Wu ,  Massud Aminpur

IPC: H01L21336

CPC classification number: H01L29/66492 ,  H01L21/26586

Abstract: The present invention is directed to a method of forming halo implants in a semiconductor device. In one illustrative embodiment, the method comprises forming a gate electrode above a surface of a semiconducting substrate, and forming a hard mask layer above the gate electrode and the substrate. The method further comprises patterning the hard mask layer to define an opening in the hard mask layer, and performing an angled implantation process through the opening in the hard mask to introduce dopant atoms into the substrate under at least a portion of the gate electrode.

Abstract translation: 本发明涉及一种在半导体器件中形成晕轮植入物的方法。 在一个说明性实施例中，该方法包括在半导体衬底的表面上方形成栅电极，以及在栅电极和衬底上形成硬掩模层。 该方法还包括图案化硬掩模层以在硬掩模层中限定开口，以及通过硬掩模中的开口进行成角度的注入工艺，以在栅电极的至少一部分下将掺杂剂原子引入衬底中。

公开(公告)号：US06391751B1

公开(公告)日：2002-05-21

申请号：US09626668

申请日：2000-07-27

Applicant: David Donggang Wu ,  William R. Roche ,  Scott D. Luning ,  Karen L. E. Turnqest

Inventor： David Donggang Wu ,  William R. Roche ,  Scott D. Luning ,  Karen L. E. Turnqest

IPC: H01L23205

CPC classification number: H01L21/28123

Abstract: The present invention is directed to a method of forming a semiconductor device. In one illustrative embodiment, the method comprises forming a layer of polysilicon, forming a masking layer above the layer of polysilicon, and patterning the masking layer to expose portions of the layer of polysilicon. The method further comprises implanting a dopant material into the exposed portions of the layer of polysilicon to convert the exposed portions of the layer of polysilicon to substantially amorphous silicon, and performing an etching process to remove the substantially amorphous silicon to define a gate electrode.

Abstract translation: 本发明涉及一种形成半导体器件的方法。 在一个说明性实施例中，该方法包括形成多晶硅层，在多晶硅层上形成掩模层，以及图案化掩模层以暴露多晶硅层的部分。 该方法还包括将掺杂剂材料注入到多晶硅层的暴露部分中以将多晶硅层的暴露部分转变为基本上非晶硅，并执行蚀刻工艺以去除基本上非晶硅以限定栅​​电极。

公开(公告)号：US06387755B1

公开(公告)日：2002-05-14

申请号：US08992616

申请日：1997-12-17

Applicant: Timothy J. Thurgate ,  Scott D. Luning

Inventor： Timothy J. Thurgate ,  Scott D. Luning

IPC: H01L21336

CPC classification number: H01L29/66825

Abstract: A system and method for providing a memory cell on a semiconductor is disclosed. The method and system include providing an oxide layer on the semiconductor and providing at least one gate stack disposed above the oxide layer. The at least one gate stack has a corner contacting the oxide layer. The method and system further include exposing at least the corner of the at least one gate stack and rounding at least the corner of the at least one gate stack.

Abstract translation: 公开了一种在半导体上提供存储单元的系统和方法。 该方法和系统包括在半导体上提供氧化物层并提供设置在氧化物层上方的至少一个栅极堆叠。 至少一个栅极堆叠具有与氧化物层接触的拐角。 所述方法和系统还包括至少暴露所述至少一个栅极堆叠的角部并至少对所述至少一个栅极叠层的角进行舍入。

公开(公告)号：US06372587B1

公开(公告)日：2002-04-16

申请号：US09568069

申请日：2000-05-10

Applicant: Jon D. Cheek ,  Scott D. Luning ,  Derick J. Wristers

Inventor： Jon D. Cheek ,  Scott D. Luning ,  Derick J. Wristers

IPC: H01L21336

CPC classification number: H01L29/66492 ,  H01L21/26586 ,  H01L29/66659 ,  H01L29/7835

Abstract: A method is provided for forming a halo implant in a substrate adjacent one side of a structure, the method including forming the structure above a surface of the substrate, the structure having first and second edges and forming a mask defining a region adjacent the structure, the mask having a thickness &tgr; above the surface and having an edge disposed a distance &dgr; from the first edge of the structure. The method also includes implanting the halo implant at an angle &agr; with respect to a direction perpendicular to the surface, wherein the tangent of the angle &agr; is at least the ratio of the distance &dgr; to the thickness &tgr;.

Abstract translation: 提供了一种用于在邻近结构的一侧的衬底中形成卤素注入的方法，所述方法包括在所述衬底的表面上方形成所述结构，所述结构具有第一和第二边缘并且形成限定邻近所述结构的区域的掩模， 该面具具有厚度＆tgr; 并且具有与结构的第一边缘相距一定距离的边缘。 该方法还包括将晕圈植入物相对于垂直于该表面的方向以角度α注入，其中角度α的切线至少为距离δ与厚度的比值。