公开(公告)号：US09059689B2

公开(公告)日：2015-06-16

申请号：US14160774

申请日：2014-01-22

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kiyoshi Kato ,  Wataru Uesugi

IPC: H03K5/04 ,  H03K5/06 ,  H03K5/05 ,  H03K5/00

CPC classification number: H03K5/06 ,  H03K5/05 ,  H03K2005/00104 ,  H03K2005/00241

Abstract: To provide a semiconductor device capable of adjusting the timing of a clock signal or a high-quality semiconductor device. The semiconductor device includes a first transistor and a circuit including a second transistor. A channel of the first transistor is formed in an oxide semiconductor layer. A first signal is input to one of a source and a drain of the first transistor. The other of the source and the drain of the first transistor is electrically connected to a gate of the second transistor. A first clock signal is input to the circuit. The circuit outputs a second clock signal. The timing of the second clock signal is different from that of the first clock signal.

Abstract translation: 提供能够调整时钟信号或高质量半导体器件的定时的半导体器件。 半导体器件包括第一晶体管和包括第二晶体管的电路。 第一晶体管的沟道形成在氧化物半导体层中。 第一信号被输入到第一晶体管的源极和漏极之一。 第一晶体管的源极和漏极中的另一个电连接到第二晶体管的栅极。 第一时钟信号被输入到电路。 电路输出第二个时钟信号。 第二时钟信号的定时与第一时钟信号的定时不同。

公开(公告)号：US20140340127A1

公开(公告)日：2014-11-20

申请号：US14277248

申请日：2014-05-14

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Hidetomo Kobayashi ,  Kiyoshi Kato ,  Wataru Uesugi

IPC: H03K3/012

CPC classification number: G09G3/00 ,  G09G2330/022 ,  H01L27/0688 ,  H01L27/1225 ,  H01L29/7833 ,  H03K19/0016

Abstract: A semiconductor device with short overhead time. The semiconductor device includes a first wiring supplied with a power supply potential, a second wiring, a switch for controlling electrical connection between the first wiring and the second wiring, a load electrically connected to the second wiring, a transistor whose source and drain are electrically connected to the second wiring, and a power management unit having functions of controlling the conduction state of the switch and controlling a gate potential of the transistor. A channel formation region of the transistor is included in an oxide semiconductor film.

Abstract translation: 具有短占空时间的半导体器件。 所述半导体器件包括供给电源电位的第一布线，第二布线，用于控制所述第一布线和所述第二布线之间的电连接的开关，电连接到所述第二布线的负载，源极和漏极电连接的晶体管 连接到第二布线，以及功率管理单元，具有控制开关的导通状态和控制晶体管的栅极电位的功能。 晶体管的沟道形成区域包括在氧化物半导体膜中。

公开(公告)号：US20130301331A1

公开(公告)日：2013-11-14

申请号：US13889957

申请日：2013-05-08

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Tatsuya Onuki ,  Wataru Uesugi

IPC: G11C14/00 ,  G11C5/06 ,  G11C5/10

CPC classification number: G11C14/0054 ,  G11C5/063 ,  G11C5/10

Abstract: To provide a semiconductor device including a volatile memory which achieves high speed operation and lower power consumption. For example, the semiconductor device includes an SRAM provided with first and second data holding portions and a non-volatile memory provided with third and fourth second data holding portions. The first data holding portion is electrically connected to the fourth data holding portion through a transistor. The second data holding portion is electrically connected to the third data holding portion through a transistor. While the SRAM holds data, the transistor is on so that both the SRAM and the non-volatile memory hold the data. Then, the transistor is turned off before supply of power is stopped, so that the data becomes non-volatile.

Abstract translation: 提供一种包括实现高速操作和较低功耗的易失性存储器的半导体器件。 例如，半导体器件包括设置有第一和第二数据保持部分的SRAM和设置有第三和第四第二数据保持部分的非易失性存储器。 第一数据保持部分通过晶体管与第四数据保持部分电连接。 第二数据保持部分通过晶体管与第三数据保持部分电连接。 当SRAM保存数据时，晶体管导通，以便SRAM和非易失性存储器都保存数据。 然后，在供电停止之前晶体管截止，使得数据变得非易失性。