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    SEMICONDUCTOR DEVICE
    3.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20150200668A1

    公开(公告)日：2015-07-16

    申请号：US14591274

    申请日：2015-01-07

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Wataru Uesugi ,  Yukio Maehashi

    IPC: H03K19/00 ,  H01L27/06 ,  H03K19/0185 ,  H01L29/786

    CPC classification number: H03K19/0013 ,  H01L27/0688 ,  H01L29/7869 ,  H01L29/78696 ,  H03K19/01855

    Abstract: The power consumption of a semiconductor device that can function as a latch circuit or the like is reduced. The semiconductor device includes a first circuit and a switch that controls conduction between an input terminal and the first circuit. The first circuit includes n second circuits (n is an integer of 2 or more) and a variable resistor. An output node of any of the n second circuits is electrically connected to an input node of the second circuit in a first stage through the variable resistor. The variable resistor can be, for example, a transistor whose channel is formed in an oxide semiconductor layer. A reduction in the number of elements or signals leads to a reduction of the power consumption of the semiconductor device.

    Abstract translation: 可以用作锁存电路等的半导体器件的功耗降低。 半导体器件包括第一电路和控制输入端和第一电路之间的导通的开关。 第一电路包括n个第二电路（n是2或更大的整数）和可变电阻器。 n个第二电路中的任一个的输出节点通过可变电阻器在第一级中电连接到第二电路的输入节点。 可变电阻器可以是例如其通道形成在氧化物半导体层中的晶体管。 元件或信号的数量的减少导致半导体器件的功耗的降低。

    MEMORY DEVICE AND SEMICONDUCTOR DEVICE
    4.
    发明申请
    MEMORY DEVICE AND SEMICONDUCTOR DEVICE 有权
    存储器件和半导体器件

    公开(公告)号：US20140269013A1

    公开(公告)日：2014-09-18

    申请号：US14208428

    申请日：2014-03-13

    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

    Inventor： Naoaki Tsutsui ,  Atsuo Isobe ,  Wataru Uesugi ,  Takuro Ohmaru

    IPC: G11C11/24

    CPC classification number: G11C11/4093 ,  G11C11/24 ,  G11C11/401 ,  G11C11/403

    Abstract: A memory device includes a first memory circuit including a silicon transistor, a selection circuit including a silicon transistor, and a second memory circuit including oxide semiconductor transistors and a storage capacitor, in which one terminal of the storage capacitor is connected to a portion where two oxide semiconductor transistors are connected in series, an output of the second memory circuit is connected to a second input terminal of the selection circuit, and an input of the second memory circuit is connected to a first input terminal of the selection circuit or an output terminal of the first memory circuit.

    Abstract translation: 存储器件包括：第一存储器电路，包括硅晶体管，包括硅晶体管的选择电路和包括氧化物半导体晶体管和存储电容器的第二存储器电路，其中存储电容器的一个端子连接到两个 氧化物半导体晶体管串联连接，第二存储电路的输出连接到选择电路的第二输入端，第二存储电路的输入端连接到选择电路的第一输入端或输出端 的第一存储器电路。

    Storage circuit and semiconductor device
    5.
    发明授权
    Storage circuit and semiconductor device 有权

    公开(公告)号：US10164612B2

    公开(公告)日：2018-12-25

    申请号：US15254373

    申请日：2016-09-01

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Yukio Maehashi ,  Seiichi Yoneda ,  Wataru Uesugi

    IPC: H03K3/289 ,  H03K3/012 ,  H03K3/356

    Abstract: The storage circuit includes first and second logic circuits, first and second transistors whose channel formation regions include an oxide semiconductor, and a capacitor. The first and second transistors are connected to each other in series, and the capacitor is connected to a connection node of the first and second transistors. The first transistor functions as a switch that controls connection between an output terminal of the first logic circuit and the capacitor. The second transistor functions as a switch that controls connection between the capacitor and an input terminal of the second logic circuit. Clock signals whose phases are inverted from each other are input to gates of the first and second transistors. Since the storage circuit has a small number of transistors and a small number of transistors controlled by the clock signals, the storage circuit is a low-power circuit.

    Logic circuit, processing unit, electronic component, and electronic device
    8.
    发明授权
    Logic circuit, processing unit, electronic component, and electronic device 有权
    逻辑电路，处理单元，电子元件和电子设备

    公开(公告)号：US09385713B2

    公开(公告)日：2016-07-05

    申请号：US14874607

    申请日：2015-10-05

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Wataru Uesugi ,  Hikaru Tamura ,  Atsuo Isobe

    IPC: H03K19/00 ,  H03K19/0185 ,  H01L29/78 ,  H01L29/04 ,  H01L27/12 ,  H01L49/02

    CPC classification number: H01L27/1207 ,  G11C7/04 ,  H01L27/1225 ,  H01L27/1255 ,  H01L28/40 ,  H01L29/04 ,  H01L29/045 ,  H01L29/7849 ,  H01L29/78648 ,  H01L29/78696 ,  H03K19/0008 ,  H03K19/018514

    Abstract: A retention circuit provided in a logic circuit enables power gating. The retention circuit includes a first terminal, a node, a capacitor, and first to third transistors. The first transistor controls electrical connection between the first terminal and an input terminal of the logic circuit. The second transistor controls electrical connection between an output terminal of the logic circuit and the node. The third transistor controls electrical connection between the node and the input terminal of the logic circuit. A gate of the first transistor is electrically connected to a gate of the second transistor. In a data retention period, the node becomes electrically floating. The voltage of the node is held by the capacitor.

    Abstract translation: 逻辑电路中提供的保持电路使能电源门控。 保持电路包括第一端子，节点，电容器以及第一至第三晶体管。 第一晶体管控制逻辑电路的第一端子和输入端子之间的电连接。 第二晶体管控制逻辑电路的输出端和节点之间的电连接。 第三晶体管控制节点与逻辑电路的输入端之间的电连接。 第一晶体管的栅极电连接到第二晶体管的栅极。 在数据保留期间，节点变为电浮动。 节点的电压由电容器保持。

    SEMICONDUCTOR DEVICE
    9.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20140266367A1

    公开(公告)日：2014-09-18

    申请号：US14199561

    申请日：2014-03-06

    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

    Inventor： Wataru Uesugi

    IPC: H03K3/012

    CPC classification number: H03K3/012 ,  H03K3/35606

    Abstract: To provide a semiconductor device which can perform a scan test and includes a logic circuit capable of reducing signal delay. The semiconductor device includes a combinational circuit, sequential circuits each holding first data supplied to the combinational circuit or second data output from the combinational circuit, first memory circuits each holding first data supplied to the corresponding sequential circuit and holding second data output from the corresponding sequential circuit, and second memory circuits electrically connecting the first memory circuits in series by supplying the first data or second data supplied from one of the first memory circuits to another one of the first memory circuits. The second memory circuit includes a first switch controlling supply of the first data or second data to the node, a capacitor electrically connected to the node, and a second switch controlling output of the first data or second data from the node.

    Abstract translation: 提供一种能够执行扫描测试并包括能够减少信号延迟的逻辑电路的半导体器件。 半导体器件包括组合电路，每个保持提供给组合电路的第一数据或从组合电路输出的第二数据的顺序电路，每个保持提供给相应的顺序电路的第一数据的第一存储器电路并且保持来自相应顺序的第二数据输出 电路和第二存储器电路通过将从第一存储器电路中的一个提供的第一数据或第二数据提供给第一存储器电路中的另一个而将第一存储器电路串联电连接。 第二存储电路包括控制向节点提供第一数据或第二数据的第一开关，电连接到该节点的电容器以及控制第一数据或第二数据从该节点输出的第二开关。

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