公开(公告)号：US20230215877A1

公开(公告)日：2023-07-06

申请号：US18119629

申请日：2023-03-09

Applicant: Sharp Kabushiki Kaisha

Inventor： Kengo HARA ,  Tohru DAITOH ,  Tetsuo KIKUCHI ,  Masahiko SUZUKI ,  Setsuji NISHIMIYA ,  Hitoshi TAKAHATA

IPC: H01L27/12 ,  H01L29/786

CPC classification number: H01L27/124 ,  H01L27/1225 ,  H01L29/78633 ,  H01L29/7869

Abstract: An active matrix substrate includes a plurality of source bus lines and a plurality of gate bus lines and a plurality of oxide semiconductor TFTs that have a plurality of pixel TFTs, each of which is associated with one of the plurality of pixel regions, and a plurality of circuit TFTs constituting a peripheral circuit, in which each of oxide semiconductor TFTs has an oxide semiconductor layer and a gate electrode disposed on a channel region of the oxide semiconductor layer via a gate insulating layer, the plurality of oxide semiconductor TFTs have a plurality of first TFTs, a plurality of second TFTs, and/or a plurality of third TFTs, and the plurality of first TFTs have the plurality of pixel TFTs, and the plurality of second TFTs and/or the plurality of third TFTs have at least a portion of the plurality of circuit TFTs.

公开(公告)号：US20220189999A1

公开(公告)日：2022-06-16

申请号：US17546105

申请日：2021-12-09

Applicant: Sharp Kabushiki Kaisha

Inventor： Kengo HARA ,  Tohru DAITOH ,  Tetsuo KIKUCHI ,  Masahiko SUZUKI ,  Setsuji NISHIMIYA ,  Hitoshi TAKAHATA

IPC: H01L27/12 ,  H01L29/786

Abstract: An active matrix substrate is provided with a plurality of oxide semiconductor TFTs including a plurality of first TFTs. An oxide semiconductor layer of each oxide semiconductor TFT includes a channel region, a source contact region, and a drain contact region. In a view from a normal direction of the substrate, the channel region is a region located between the source contact region and the drain contact region and overlapping a gate electrode, and the channel region includes a first end portion and a second end portion that oppose each other and extend in a first direction from the source contact region side toward the drain contact region side, a source side end portion that is located on the source contact region side of the first and second end portions and extends in a second direction that intersects the first direction, and a drain side end portion that is located on the drain contact region side of the first and second end portions and extends in the second direction. Each first TFT further includes a light blocking layer located between the oxide semiconductor layer and the substrate. In a view from the normal direction of the substrate, the light blocking layer includes an opening region that overlaps part of the channel region and a light blocking region that overlaps another part of the channel region. In a view from the normal direction of the substrate, the light blocking region includes a first light blocking portion that extends in the first direction over the first end portion of the channel region and a second light blocking portion that extends in the first direction over the second end portion of the channel region; each of the first light blocking portion and the second light blocking portion includes a first edge portion and a second edge portion that oppose each other and extend in the first direction; at least part of the first edge portion overlaps the channel region; and the second edge portion is located on an outer side of the channel region and does not overlap the channel region.

公开(公告)号：US20220077318A1

公开(公告)日：2022-03-10

申请号：US17524766

申请日：2021-11-12

Applicant: Sharp Kabushiki Kaisha

Inventor： Tetsuo KIKUCHI ,  Masahiko SUZUKI ,  Setsuji NISHIMIYA ,  Teruyuki UEDA ,  Masamitsu YAMANAKA ,  Tohru DAITOH ,  Hajime IMAI ,  Kengo HARA

IPC: H01L29/786 ,  H01L29/417 ,  G02F1/1368 ,  H01L21/02 ,  H01L21/306 ,  H01L29/66

Abstract: A semiconductor device includes a thin film transistor, wherein: a semiconductor layer of the thin film transistor has a layered structure including a lower oxide semiconductor layer including In, Ga, Zn and Sn and an upper oxide semiconductor layer arranged on the lower oxide semiconductor layer and including In, Ga and Zn; a thickness of the lower oxide semiconductor layer is 20 nm or less; an atomic ratio of Sn with respect to all metal elements of the lower oxide semiconductor layer is 5% or more; the upper oxide semiconductor layer includes no Sn, or an atomic ratio of Sn with respect to all metal elements of the upper oxide semiconductor layer is smaller than an atomic ratio of Sn with respect to all metal elements of the lower oxide semiconductor layer; and a first angle θ1 between a side surface and a lower surface of the lower oxide semiconductor layer is smaller than a second angle θ2 between a side surface and a lower surface of the upper oxide semiconductor layer.

公开(公告)号：US20210390920A1

公开(公告)日：2021-12-16

申请号：US17401396

申请日：2021-08-13

Applicant: Sharp Kabushiki Kaisha

Inventor： Tetsuo KIKUCHI ,  Hideki KITAGAWA ,  Hajime IMAI ,  Toshikatsu ITOH ,  Masahiko SUZUKI ,  Teruyuki UEDA ,  Kengo HARA ,  Setsuji NISHIMIYA ,  Tohru DAITOH

IPC: G09G3/36 ,  G02F1/1362 ,  H01L27/32

Abstract: According to an embodiment of the present invention, an active matrix substrate (100) includes a display region (DR) defined by a plurality of pixel regions (P) arranged in a matrix and a peripheral region (FR) located around the display region. The active matrix substrate includes a substrate (1), a first TFT (10), and a second TFT (20). The first TFT is supported by the substrate and disposed in the peripheral region. The second TFT is supported by the substrate and disposed in the display region. The first TFT includes a crystalline silicon semiconductor layer (11), which is an active layer. The second TFT includes an oxide semiconductor layer (21), which is an active layer. The first TFT and the second TFT each have a top-gate structure.

公开(公告)号：US20210249445A1

公开(公告)日：2021-08-12

申请号：US17156769

申请日：2021-01-25

Applicant: Sharp Kabushiki Kaisha

Inventor： Masahiko SUZUKI ,  Tetsuo KIKUCHI ,  Hideki KITAGAWA ,  Setsuji NISHIMIYA ,  Kengo HARA ,  Hitoshi TAKAHATA ,  Tohru DAITOH

IPC: H01L27/12 ,  H01L29/786

Abstract: An active matrix substrate includes a plurality of gate bus lines, a plurality of source bus lines located closer to the substrate side; a lower insulating layer that covers the source bus lines; an interlayer insulating layer that covers the gate bus lines; a plurality of oxide semiconductor TFTs disposed in association with respective pixel regions; a pixel electrode disposed in each of the pixel regions; and a plurality of source contact portions each of which electrically connects one of the oxide semiconductor TFTs to the corresponding one of the source bus lines, in which each of the oxide semiconductor TFTs includes an oxide semiconductor layer disposed on the lower insulating layer, a gate electrode disposed on a portion of the oxide semiconductor layer, and a source electrode formed of a conductive film, and each of the source contact portions includes a source contact hole, and a connection electrode.

公开(公告)号：US20200227560A1

公开(公告)日：2020-07-16

申请号：US16491248

申请日：2018-03-01

Applicant: Sharp Kabushiki Kaisha

Inventor： Toshikatsu ITOH ,  Hajime IMAI ,  Hideki KITAGAWA ,  Tetsuo KIKUCHI ,  Setsuji NISHIMIYA ,  Teruyuki UEDA ,  Kengo HARA ,  Tohru DAITOH ,  Masahiko SUZUKI

IPC: H01L29/786 ,  H01L27/12

Abstract: A semiconductor device (100) of an embodiment of the present invention includes: a substrate (1); a plurality of TFTs (10) supported by the substrate; and a protecting layer (20) covering the plurality of TFTs. Each of the TFTs is a back channel etch type TFT which includes a gate electrode (2), a gate insulating layer (3), an oxide semiconductor layer (4), a source electrode (5) and a drain electrode (6). The gate electrode includes a tapered portion (TP) defined by a lateral surface (2s) which has a tapered shape. When viewed in a direction normal to a substrate surface, a periphery of the oxide semiconductor layer includes an edge (4e1, 4e2) which extends in a direction intersecting a channel width direction (DW) and which is more internal than an edge of the gate electrode in the channel width direction. The distance from the edge of the oxide semiconductor layer to an inside end of the tapered portion is not less than 1.5 μm.

公开(公告)号：US20200089037A1

公开(公告)日：2020-03-19

申请号：US16571325

申请日：2019-09-16

Applicant: Sharp Kabushiki Kaisha

Inventor： Hikaru YOSHINO ,  Junichi MORINAGA ,  Tetsuo KIKUCHI ,  Kengo HARA

IPC: G02F1/1333 ,  G02F1/1362 ,  H01L27/12

Abstract: A method for manufacturing an active matrix substrate including a thin film transistor disposed for each pixel, and a first electrode and a first wiring line for touchscreen panel function includes: (A) a step of forming an oxide semiconductor layer, a gate insulating layer, and a gate electrode on a substrate; (B) a step of forming an insulating layer covering the gate electrode, the gate insulating layer, and the oxide semiconductor layer, and having a source-side aperture and a drain-side aperture through which portions of the oxide semiconductor layer are exposed; (C) a step of forming a source electrode within the source-side aperture and a drain electrode within the drain-side aperture; (D) a step of forming an interlayer insulating layer including an organic insulating layer and having a first contact hole through which a portion of the drain electrode is exposed; (E) a step of forming a first transparent electrically conductive film on the interlayer insulating layer and within the first contact hole; (F) a step of forming by using a metal film, on a portion of the first transparent electrically conductive film, an upper wiring portion to become an upper layer of the first wiring line; (G) a step of patterning the first transparent electrically conductive film to make a pixel electrode and form a lower wiring portion to become a lower layer of the first wiring line; (H) a step of forming a dielectric layer covering the pixel electrode and the first wiring line and having a second contact hole through which a portion of the first wiring line is exposed; and (I) a step of forming, on the dielectric layer and within the second contact hole, a common electrode which is electrically connected to the first wiring line within the second contact hole. When viewed from a normal direction of the substrate, a bottom face of the first contact hole at least partially overlaps a bottom face of the drain-side aperture, and a bottom face of the second contact hole at least partially overlaps a bottom face of the source-side aperture.

公开(公告)号：US20190172843A1

公开(公告)日：2019-06-06

申请号：US16081455

申请日：2017-02-27

Applicant: Sharp Kabushiki Kaisha

Inventor： Tokuo YOSHIDA ,  Takuya WATANABE ,  Akira TAGAWA ,  Yasuaki IWASE ,  Kengo HARA

IPC: H01L27/12 ,  G02F1/1368 ,  G02F1/1362 ,  G09G3/36 ,  G11C19/28

Abstract: An active matrix substrate is provided with a gate driver including a multi-stage shift register (240). Each stage of the multi-stage shift register has a plurality of oxide semiconductor TFTs, a first input terminal for receiving a set signal, a second input terminal for receiving a clock signal, a third input terminal for receiving a clear signal, and an output terminal for outputting a gate output signal to one of the plurality of gate bus lines. The clock signal and the clear signal have the same high-level potential, and the clock signal and the clear signal have the same low-level potential. The plurality of oxide semiconductor TFTs include a first TFT (101) having a back-gate structure. The main gate electrode of the first TFT (101) is coupled to the third input terminal or a negative power supply voltage VSS. The back-gate electrode of the first TFT has a potential set to a positive power supply voltage VDD or a ground potential GND.

公开(公告)号：US20190148558A1

公开(公告)日：2019-05-16

申请号：US16182643

申请日：2018-11-07

Applicant: Sharp Kabushiki Kaisha

Inventor： Masahiko SUZUKI ,  Tohru DAITOH ,  Hajime IMAI ,  Tetsuo KIKUCHI ,  Setsuji NISHIMIYA ,  Teruyuki UEDA ,  Kengo HARA

IPC: H01L29/786 ,  H01L29/10

CPC classification number: H01L29/7869 ,  H01L29/1054 ,  H01L29/78648

Abstract: A semiconductor device includes a substrate and an oxide semiconductor TFT including an oxide semiconductor layer supported by the substrate and having a multilayer structure including a protective oxide semiconductor layer and a channel oxide semiconductor layer disposed closer to the substrate than the protective oxide semiconductor layer, an upper insulating layer on the oxide semiconductor layer, an upper gate electrode disposed on the upper insulating layer, an interlayer insulating layer covering the oxide semiconductor layer and the upper gate electrode, and first and second electrodes electrically connected to the oxide semiconductor layer, wherein a first opening extends through at least the interlayer insulating layer and the protective oxide semiconductor layer, and exposes a portion of the channel oxide semiconductor layer, and the first electrode is disposed on the interlayer insulating layer and within the first opening, and is in direct contact with, within the first opening, the portion.

公开(公告)号：US20190103494A1

公开(公告)日：2019-04-04

申请号：US16142082

申请日：2018-09-26

Applicant: Sharp Kabushiki Kaisha

Inventor： Kengo HARA ,  Tohru DAITOH ,  Hajime IMAI ,  Tetsuo KIKUCHI ,  Masahiko SUZUKI ,  Setsuji NISHIMIYA ,  Teruyuki UEDA

IPC: H01L29/786 ,  H01L29/49 ,  H01L29/51 ,  H01L29/423

CPC classification number: H01L29/78648 ,  G02F1/136286 ,  G02F1/1368 ,  H01L27/1225 ,  H01L27/124 ,  H01L29/24 ,  H01L29/42364 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/513 ,  H01L29/518 ,  H01L29/7869 ,  H01L29/78696

Abstract: A thin film transistor includes a channel section formed from semiconductor material, a source electrode connected to one end of the channel section, a drain electrode connected to another end of the channel section, an upper gate electrode included in an upper layer than the channel section and overlapping the channel section, a lower gate electrode included in a lower layer than the channel section and overlapping the channel section, an upper gate insulation film disposed between the upper gate electrode and the channel section, and a lower gate insulation film disposed between the lower gate electrode and the channel section and having a film thickness relatively greater than that of the upper gate insulation film.