公开(公告)号：US20210294138A1

公开(公告)日：2021-09-23

申请号：US16336483

申请日：2017-09-19

Applicant: Sharp Kabushiki Kaisha

Inventor： Hideki KITAGAWA ,  Tohru DAITOH ,  Hajime IMAI ,  Tetsuo KIKUCHI ,  Masahiko SUZUKI ,  Toshikatsu ITOH ,  Teruyuki UEDA ,  Setsuji NISHIMIYA ,  Kengo HARA

IPC: G02F1/1368 ,  H01L27/12

Abstract: A pixel area in the active matrix substrate 100 includes a thin film transistor 101 that has an oxide semiconductor layer 7, an inorganic insulating layer 11 and an organic insulating layer 12 that cover a thin film transistor, a common electrode 15, a dielectric layer 17 that primarily contains silicon nitride, and a pixel electrode 19. The inorganic insulating layer has a multi-layered structure that includes a silicon oxide layer and a silicon nitride layer. A pixel electrode 10 is brought into contact with a drain electrode 9 within a pixel contact hole. The pixel contact hole is configured with a first opening portion, a second opening portion, and a third opening portion that are formed in the inorganic insulating layer 11, the organic insulating layer 12, and the dielectric layer 17, respectively. A flank surface of the first opening portion and a flank surface of the second opening portion are aligned. The flank surface of the second opening portion includes a first portion 121 that is inclined at a first angle θ1 with respect to a substrate, a second portion 122 that is positioned above the first portion and is inclined at a second angle θ2 that is greater than the first angle, and a border 120 that is positioned between the first portion and the second portion and of which an inclination angle with respect to the substrate discontinuously changes.

公开(公告)号：US20200264485A1

公开(公告)日：2020-08-20

申请号：US16788423

申请日：2020-02-12

Applicant: Sharp Kabushiki Kaisha

Inventor： Setsuji NISHIMIYA ,  Tohru DAITOH ,  Hajime IMAI ,  Tetsuo KIKUCHI ,  Masahiko SUZUKI ,  Teruyuki UEDA ,  Masamitsu YAMANAKA ,  Kengo HARA ,  Hitoshi TAKAHATA

IPC: G02F1/1362 ,  G02F1/1343 ,  G02F1/1368 ,  G02F1/1333

Abstract: An active matrix substrate 10 includes: switching elements 120 that are connected with gate lines and data lines provided on a substrate; pixel electrodes 130 that are connected with the switching elements 120; counter electrodes 140 that overlap with the pixel electrodes 130 when viewed in a plan view; a flattening film 154; and lines 142. The flattening film 154 covers the switching elements 120, and first contact holes CH1 that pass through the flattening film 154 are formed at positions that overlap with the lines 142 when viewed in a plan view. The pixel electrodes 130 and the counter electrodes 140 are arranged so that each of the same partially covers the flattening film 154. The line 142 and the counter electrode 140 are connected with each other in the first contact hole CH1.

公开(公告)号：US20190326443A1

公开(公告)日：2019-10-24

申请号：US16336481

申请日：2017-09-21

Applicant: Sharp Kabushiki Kaisha

Inventor： Masahiko SUZUKI ,  Hajime IMAI ,  Hideki KITAGAWA ,  Tetsuo KIKUCHI ,  Setsuji NISHIMIYA ,  Teruyuki UEDA ,  Kengo HARA ,  Tohru DAITOH ,  Toshikatsu ITOH

IPC: H01L29/786 ,  H01L29/24 ,  H01L21/02 ,  H01L29/66 ,  H01L27/12 ,  G02F1/1345 ,  G02F1/1368 ,  G02F1/1343

Abstract: A semiconductor device includes a thin film transistor including a semiconductor layer, a gate electrode, a gate insulating layer, a source electrode, a drain electrode, the semiconductor layer includes a layered structure including a first oxide semiconductor layer including In and Zn, in which an atomic ratio of In with respect to all metallic elements included in the first oxide semiconductor layer is higher than an atomic ratio of Zn, a second oxide semiconductor layer including In and Zn, in which an atomic ratio of Zn with respect to all metallic elements included in the second oxide semiconductor layer is higher than an atomic ratio of In, and an intermediate oxide semiconductor layer arranged between the first oxide semiconductor layer and the second oxide semiconductor layer, and the first and second oxide semiconductor layers are crystalline oxide semiconductor layers, and the intermediate oxide semiconductor layer is an amorphous oxide semiconductor layer, and the first oxide semiconductor layer is arranged nearer to the gate insulating layer than the second oxide semiconductor layer.

公开(公告)号：US20190103421A1

公开(公告)日：2019-04-04

申请号：US16132509

申请日：2018-09-17

Applicant: Sharp Kabushiki Kaisha

Inventor： Tetsuo KIKUCHI ,  Tohru DAITOH ,  Hajime IMAI ,  Masahiko SUZUKI ,  Setsuji NISHIMIYA ,  Teruyuki UEDA ,  Kengo HARA

IPC: H01L27/12 ,  G02F1/1345 ,  G02F1/1362 ,  G02F1/1343 ,  G02F1/1333 ,  G06F3/041

Abstract: A TFT array substrate includes gate electrodes constructed from a first metal film, a first insulating film on the first metal film, channels constructed from a semiconductor film on the first insulating film, source electrodes constructed from a second metal film on the semiconductor film, drain electrodes constructed from the second metal film, pixel electrodes constructed from portions of the semiconductor film having reduced resistances, a second insulating film on the semiconductor film and the second metal film, and a common electrode constructed from a transparent electrode film on the second insulating film. The channels overlap the gate electrodes. The source electrodes and the drain electrodes are connected to first ends and second ends of the channels, respectively. The pixel electrodes are connected to the drain electrodes. The second insulating film includes sections overlapping the pixel electrodes without openings. The common electrode overlaps at least the pixel electrodes.

公开(公告)号：US20170358674A1

公开(公告)日：2017-12-14

申请号：US15531385

申请日：2015-11-19

Applicant: Sharp Kabushiki Kaisha

Inventor： Tetsuo KIKUCHI ,  Hajime IMAI ,  Hisao OCHI ,  Tetsuo FUJITA ,  Hideki KITAGAWA ,  Masahiko SUZUKI ,  Shingo KAWASHIMA ,  Tohru DAITOH

IPC: H01L29/786 ,  H01L21/02 ,  G02F1/1362 ,  H01L21/28 ,  G02F1/1368 ,  H01L29/417 ,  G02F1/1333 ,  G02F1/1345

Abstract: A semiconductor device includes a substrate and a thin film transistor supported by the substrate. The thin film transistor includes a gate electrode, an oxide semiconductor layer, a gate insulating layer provided between the gate electrode and the oxide semiconductor layer, and source and drain electrodes electrically connected to the oxide semiconductor layer. The gate insulating layer includes a first portion which is covered with the oxide semiconductor layer and a second portion which is adjacent to the first portion and which is not covered with any of the oxide semiconductor layer, the source electrode and the drain electrode. The second portion is smaller in thickness than the first portion, and the difference in thickness between the second portion and the first portion is more than 0 nm and not more than 50 nm.

公开(公告)号：US20240339460A1

公开(公告)日：2024-10-10

申请号：US18746280

申请日：2024-06-18

Applicant: Sharp Kabushiki Kaisha

Inventor： Kengo HARA ,  Tohru DAITOH ,  Tetsuo KIKUCHI ,  Masahiko SUZUKI ,  Setsuji NISHIMIYA ,  Hitoshi TAKAHATA

IPC: H01L27/12 ,  H01L29/786

CPC classification number: H01L27/124 ,  H01L27/1225 ,  H01L29/78633 ,  H01L29/7869

Abstract: An active matrix substrate includes a plurality of source bus lines and a plurality of gate bus lines and a plurality of oxide semiconductor TFTs that have a plurality of pixel TFTs, each of which is associated with one of the plurality of pixel regions, and a plurality of circuit TFTs constituting a peripheral circuit, in which each of oxide semiconductor TFTs has an oxide semiconductor layer and a gate electrode disposed on a channel region of the oxide semiconductor layer via a gate insulating layer, the plurality of oxide semiconductor TFTs have a plurality of first TFTs, a plurality of second TFTs, and/or a plurality of third TFTs, and the plurality of first TFTs have the plurality of pixel TFTs, and the plurality of second TFTs and/or the plurality of third TFTs have at least a portion of the plurality of circuit TFTs.

公开(公告)号：US20240297181A1

公开(公告)日：2024-09-05

申请号：US18663479

申请日：2024-05-14

Applicant: Sharp Kabushiki Kaisha

Inventor： Masahiko SUZUKI ,  Tetsuo KIKUCHI ,  Hideki KITAGAWA ,  Setsuji NISHIMIYA ,  Kengo HARA ,  Hitoshi TAKAHATA ,  Tohru DAITOH

IPC: H01L27/12 ,  H01L29/786

CPC classification number: H01L27/124 ,  H01L27/1222 ,  H01L27/1225 ,  H01L27/1237 ,  H01L27/127 ,  H01L29/7869 ,  H01L29/78696

Abstract: An active matrix substrate includes a plurality of gate bus lines, a plurality of source bus lines located closer to the substrate side; a lower insulating layer that covers the source bus lines; an interlayer insulating layer that covers the gate bus lines; a plurality of oxide semiconductor TFTs disposed in association with respective pixel regions; a pixel electrode disposed in each of the pixel regions; and a plurality of source contact portions each of which electrically connects one of the oxide semiconductor TFTs to the corresponding one of the source bus lines, in which each of the oxide semiconductor TFTs includes an oxide semiconductor layer disposed on the lower insulating layer, a gate electrode disposed on a portion of the oxide semiconductor layer, and a source electrode formed of a conductive film, and each of the source contact portions includes a source contact hole, and a connection electrode.

公开(公告)号：US20230215877A1

公开(公告)日：2023-07-06

申请号：US18119629

申请日：2023-03-09

Applicant: Sharp Kabushiki Kaisha

Inventor： Kengo HARA ,  Tohru DAITOH ,  Tetsuo KIKUCHI ,  Masahiko SUZUKI ,  Setsuji NISHIMIYA ,  Hitoshi TAKAHATA

IPC: H01L27/12 ,  H01L29/786

CPC classification number: H01L27/124 ,  H01L27/1225 ,  H01L29/78633 ,  H01L29/7869

Abstract: An active matrix substrate includes a plurality of source bus lines and a plurality of gate bus lines and a plurality of oxide semiconductor TFTs that have a plurality of pixel TFTs, each of which is associated with one of the plurality of pixel regions, and a plurality of circuit TFTs constituting a peripheral circuit, in which each of oxide semiconductor TFTs has an oxide semiconductor layer and a gate electrode disposed on a channel region of the oxide semiconductor layer via a gate insulating layer, the plurality of oxide semiconductor TFTs have a plurality of first TFTs, a plurality of second TFTs, and/or a plurality of third TFTs, and the plurality of first TFTs have the plurality of pixel TFTs, and the plurality of second TFTs and/or the plurality of third TFTs have at least a portion of the plurality of circuit TFTs.

公开(公告)号：US20220189999A1

公开(公告)日：2022-06-16

申请号：US17546105

申请日：2021-12-09

Applicant: Sharp Kabushiki Kaisha

Inventor： Kengo HARA ,  Tohru DAITOH ,  Tetsuo KIKUCHI ,  Masahiko SUZUKI ,  Setsuji NISHIMIYA ,  Hitoshi TAKAHATA

IPC: H01L27/12 ,  H01L29/786

Abstract: An active matrix substrate is provided with a plurality of oxide semiconductor TFTs including a plurality of first TFTs. An oxide semiconductor layer of each oxide semiconductor TFT includes a channel region, a source contact region, and a drain contact region. In a view from a normal direction of the substrate, the channel region is a region located between the source contact region and the drain contact region and overlapping a gate electrode, and the channel region includes a first end portion and a second end portion that oppose each other and extend in a first direction from the source contact region side toward the drain contact region side, a source side end portion that is located on the source contact region side of the first and second end portions and extends in a second direction that intersects the first direction, and a drain side end portion that is located on the drain contact region side of the first and second end portions and extends in the second direction. Each first TFT further includes a light blocking layer located between the oxide semiconductor layer and the substrate. In a view from the normal direction of the substrate, the light blocking layer includes an opening region that overlaps part of the channel region and a light blocking region that overlaps another part of the channel region. In a view from the normal direction of the substrate, the light blocking region includes a first light blocking portion that extends in the first direction over the first end portion of the channel region and a second light blocking portion that extends in the first direction over the second end portion of the channel region; each of the first light blocking portion and the second light blocking portion includes a first edge portion and a second edge portion that oppose each other and extend in the first direction; at least part of the first edge portion overlaps the channel region; and the second edge portion is located on an outer side of the channel region and does not overlap the channel region.

公开(公告)号：US20220157855A1

公开(公告)日：2022-05-19

申请号：US17665750

申请日：2022-02-07

Applicant: Sharp Kabushiki Kaisha

Inventor： Hajime IMAI ,  Tohru DAITOH ,  Tetsuo KIKUCHI ,  Masamitsu YAMANAKA ,  Yoshihito HARA ,  Tatsuya KAWASAKI ,  Masahiko SUZUKI ,  Setsuji NISHIMIYA

IPC: H01L27/12 ,  H01L29/24 ,  H01L29/417 ,  H01L29/786 ,  H01L21/02 ,  H01L21/465 ,  H01L29/66 ,  G02F1/1368 ,  G02F1/1362 ,  G02F1/1343

Abstract: The oxide semiconductor layer is electrically connected to a source electrode or the source bus line within the source opening formed in the lower insulating layer, each wiring line connection section includes a lower conductive portion formed using the first conductive film, the lower insulating layer extending over the lower conductive portion, an oxide connection layer formed using an oxide film the same as the oxide semiconductor layer and electrically connected to the lower conductive portion within the lower opening formed in the lower insulating layer, an insulating layer covering the oxide connection layer, and an upper conductive portion electrically connected to the oxide connection layer within the upper opening formed in the insulating layer, wherein the oxide connection layer includes a region lower in a specific resistance than the channel region of the oxide semiconductor layer.