公开(公告)号：US20190072790A1

公开(公告)日：2019-03-07

申请号：US16055205

申请日：2018-08-06

Applicant: Sharp Kabushiki Kaisha

Inventor： Masaki MAEDA ,  Yoshihito HARA ,  Tohru DAITOH ,  Hajime IMAI ,  Hideki KITAGAWA ,  Toshikatsu ITOH ,  Tatsuya KAWASAKI

IPC: G02F1/1333 ,  G02F1/1362 ,  H01L23/544 ,  H01L21/3213

Abstract: A method of producing a substrate having an alignment mark includes a process of forming a lower layer side metal film on a substrate and forming a lower layer side alignment mark base having a lower layer side alignment mark that is a hole, a process of forming an upper layer side metal film on the substrate and the lower layer side metal film, a process of forming a photoresist film on the upper layer side metal film and forming a lower layer side alignment mark overlapping portion overlapping a part of the lower layer side alignment mark with patterning, an etching process of removing with etching selectively portions of the lower and upper layer side metal films not overlapping the lower layer side alignment mark overlapping portion and forming an upper layer side alignment mark that is the upper layer side metal film, and a photoresist removing process.

公开(公告)号：US20210183899A1

公开(公告)日：2021-06-17

申请号：US17118666

申请日：2020-12-11

Applicant: Sharp Kabushiki Kaisha

Inventor： Hajime IMAI ,  Tohru DAITOH ,  Teruyuki UEDA ,  Yoshihito HARA ,  Masaki MAEDA ,  Tatsuya KAWASAKI ,  Yoshiharu HIRATA ,  Tetsuo KIKUCHI

IPC: H01L27/12

Abstract: An active matrix substrate includes a plurality of source bus lines, a lower insulating layer covering the source bus lines, a plurality of gate bus lines formed above the lower insulating layer, and an oxide semiconductor TFT disposed to correspond to each pixel area. The oxide semiconductor TFT includes an oxide semiconductor layer disposed on the lower insulating layer, and a gate electrode disposed above the oxide semiconductor layer. The gate electrode is formed in a different layer from the gate bus lines, and is disposed to be separated from another gate electrode disposed in an adjacent pixel area. The gate electrode is covered by an interlayer insulating layer. The gate bus line is disposed on the interlayer insulating layer and in a gate contact hole formed in the interlayer insulating layer, and is connected to the gate electrode in the gate contact hole.

公开(公告)号：US20190113789A1

公开(公告)日：2019-04-18

申请号：US16161114

申请日：2018-10-16

Applicant: Sharp Kabushiki Kaisha

Inventor： Toshikatsu ITOH ,  Tohru DAITOH ,  Hajime IMAI ,  Masaki MAEDA ,  Hideki KITAGAWA ,  Yoshihito HARA ,  Tatsuya KAWASAKI

IPC: G02F1/1333 ,  H01L27/12 ,  H01L21/3213 ,  G02F1/1343 ,  G02F1/1362

Abstract: A method of manufacturing a display panel substrate includes a transparent conductive film formation step of forming a transparent conductive film on a flattening film that covers a switching component disposed on a substrate, a metallic film formation step of forming a metallic film so as to cover the transparent conductive film after the transparent conductive film formation step, a line formation step of forming a line by etching the metallic film after the metallic film formation step, and a transparent electrode formation step of forming a transparent electrode that is connected to the line by etching the transparent conductive film after the wire formation step.

公开(公告)号：US20220157855A1

公开(公告)日：2022-05-19

申请号：US17665750

申请日：2022-02-07

Applicant: Sharp Kabushiki Kaisha

Inventor： Hajime IMAI ,  Tohru DAITOH ,  Tetsuo KIKUCHI ,  Masamitsu YAMANAKA ,  Yoshihito HARA ,  Tatsuya KAWASAKI ,  Masahiko SUZUKI ,  Setsuji NISHIMIYA

IPC: H01L27/12 ,  H01L29/24 ,  H01L29/417 ,  H01L29/786 ,  H01L21/02 ,  H01L21/465 ,  H01L29/66 ,  G02F1/1368 ,  G02F1/1362 ,  G02F1/1343

Abstract: The oxide semiconductor layer is electrically connected to a source electrode or the source bus line within the source opening formed in the lower insulating layer, each wiring line connection section includes a lower conductive portion formed using the first conductive film, the lower insulating layer extending over the lower conductive portion, an oxide connection layer formed using an oxide film the same as the oxide semiconductor layer and electrically connected to the lower conductive portion within the lower opening formed in the lower insulating layer, an insulating layer covering the oxide connection layer, and an upper conductive portion electrically connected to the oxide connection layer within the upper opening formed in the insulating layer, wherein the oxide connection layer includes a region lower in a specific resistance than the channel region of the oxide semiconductor layer.

公开(公告)号：US20200312885A1

公开(公告)日：2020-10-01

申请号：US16830313

申请日：2020-03-26

Applicant: Sharp Kabushiki Kaisha

Inventor： Hajime IMAI ,  Tohru DAITOH ,  Tetsuo KIKUCHI ,  Masamitsu YAMANAKA ,  Yoshihito HARA ,  Tatsuya KAWASAKI ,  Masahiko SUZUKI ,  Setsuji NISHIMIYA

IPC: H01L27/12 ,  H01L29/24 ,  H01L29/417 ,  H01L29/786 ,  H01L21/02 ,  H01L21/465 ,  H01L29/66 ,  G02F1/1368 ,  G02F1/1362 ,  G02F1/1343

Abstract: The oxide semiconductor layer is electrically connected to a source electrode or the source bus line within the source opening formed in the lower insulating layer, each wiring line connection section includes a lower conductive portion formed using the first conductive film, the lower insulating layer extending over the lower conductive portion, an oxide connection layer formed using an oxide film the same as the oxide semiconductor layer and electrically connected to the lower conductive portion within the lower opening formed in the lower insulating layer, an insulating layer covering the oxide connection layer, and an upper conductive portion electrically connected to the oxide connection layer within the upper opening formed in the insulating layer, wherein the oxide connection layer includes a region lower in a specific resistance than the channel region of the oxide semiconductor layer.

公开(公告)号：US20190079364A1

公开(公告)日：2019-03-14

申请号：US16124223

申请日：2018-09-07

Applicant: Sharp Kabushiki Kaisha

Inventor： Yoshihito HARA ,  Tohru DAITOH ,  Hajime IMAI ,  Masaki MAEDA ,  Hideki KITAGAWA ,  Toshikatsu ITOH ,  Tatsuya KAWASAKI

IPC: G02F1/1362 ,  H01L33/42 ,  H01L21/477 ,  H01L21/02 ,  H01L33/00 ,  H01L33/28

Abstract: A method includes a pixel electrode forming process of forming a pixel electrode formed from a transparent electrode film on a gate insulation film that covers a gate electrode, a semiconductor film forming process being performed after the pixel electrode forming process and forming a semiconductor film on the gate insulation film such that a part of the semiconductor film covers the pixel electrode, an annealing process being performed after the semiconductor film forming process and processing the semiconductor film with annealing, and an etching process being performed after the annealing process and processing the semiconductor film with etching such that a channel section overlapping the gate electrode is formed in a same layer as the pixel electrode. The etching and the annealing performed on one of the transparent electrode film and the semiconductor film is less likely to adversely affect another one of the films.

公开(公告)号：US20210143184A1

公开(公告)日：2021-05-13

申请号：US16628048

申请日：2018-06-28

Applicant: Sharp Kabushiki Kaisha

Inventor： Tatsuya KAWASAKI ,  Hideki KITAGAWA ,  Yoshihito HARA ,  Masaki MAEDA ,  Toshikatsu ITOH ,  Hajime IMAI ,  Tohru DAITOH

IPC: H01L27/12 ,  G02F1/1368

Abstract: The present invention provides a thin-film transistor array substrate that prevents semiconductor layers of thin-film transistor elements from having step disconnection even when the frame width is reduced. The thin-film transistor array substrate of the present invention includes a thin-film transistor element in a pixel region and a terminal in a terminal region. The thin-film transistor array substrate sequentially includes a support, an insulating layer, a gate electrode, a gate insulating layer, and a semiconductor layer in a cross-sectional view of the pixel region. A region with the insulating layer encompasses a region with the semiconductor layer in a plan view of the pixel region. The thin-film transistor array substrate sequentially includes the support, a lead line extending from the terminal, and the insulating layer in a cross-sectional view of the terminal region.

公开(公告)号：US20210124220A1

公开(公告)日：2021-04-29

申请号：US17075750

申请日：2020-10-21

Applicant: Sharp Kabushiki Kaisha

Inventor： Yoshiharu HIRATA ,  Yoshihito HARA ,  Hideki KITAGAWA ,  Tatsuya KAWASAKI ,  Masaki MAEDA ,  Teruyuki UEDA ,  Yoshimasa CHIKAMA ,  Hajime IMAI ,  Tohru DAITOH

IPC: G02F1/1343 ,  G02F1/1368 ,  G02F1/1333 ,  G02F1/1362 ,  G02F1/1337 ,  G06F3/041

Abstract: An active matrix substrate includes TFTs, an interlayer insulating layer, a common electrode, a first dielectric layer, pixel electrodes, a second dielectric layer, and touch wirings, in which each of the pixel electrodes at least partially overlaps the common electrode via the first dielectric layer, so that an auxiliary capacitance including each of the pixel electrodes, the common electrode, and the first dielectric layer is formed, the touch sensor electrodes include a first electrode, the touch wirings include a first wiring and a second wiring in the touch sensor electrodes, the second wiring extends to the other electrode across the first electrode when viewed from a normal direction, and a portion of the second wiring overlaps the first electrode via the first and the second dielectric layers, so that a touch wiring capacitance including the second wiring, the first electrode, the first and the second dielectric layers is formed.

公开(公告)号：US20230307465A1

公开(公告)日：2023-09-28

申请号：US18199142

申请日：2023-05-18

Applicant: Sharp Kabushiki Kaisha

Inventor： Hajime IMAI ,  Tohru DAITOH ,  Teruyuki UEDA ,  Yoshihito HARA ,  Masaki MAEDA ,  Tatsuya KAWASAKI ,  Yoshiharu HIRATA ,  Tetsuo KIKUCHI

IPC: H01L27/12

CPC classification number: H01L27/124 ,  H01L27/1225 ,  H01L27/127

Abstract: An active matrix substrate includes a plurality of source bus lines, a lower insulating layer covering the source bus lines, a plurality of gate bus lines formed above the lower insulating layer, and an oxide semiconductor TFT disposed to correspond to each pixel area. The oxide semiconductor TFT includes an oxide semiconductor layer disposed on the lower insulating layer, and a gate electrode disposed above the oxide semiconductor layer. The gate electrode is formed in a different layer from the gate bus lines, and is disposed to be separated from another gate electrode disposed in an adjacent pixel area. The gate electrode is covered by an interlayer insulating layer. The gate bus line is disposed on the interlayer insulating layer and in a gate contact hole formed in the interlayer insulating layer, and is connected to the gate electrode in the gate contact hole.

公开(公告)号：US20210384276A1

公开(公告)日：2021-12-09

申请号：US17338750

申请日：2021-06-04

Applicant: Sharp Kabushiki Kaisha

Inventor： Hajime IMAI ,  Tohru DAITOH ,  Teruyuki UEDA ,  Yoshihito HARA ,  Masaki MAEDA ,  Tatsuya KAWASAKI ,  Yoshiharu HIRATA

IPC: H01L27/32 ,  H01L29/786 ,  H01L29/66

Abstract: An active matrix substrate includes a first TFT and a second TFT, in which the first TFT includes a first oxide semiconductor layer and a first gate electrode arranged on a part of the first oxide semiconductor layer with a first gate insulating layer interposed therebetween, the first gate insulating layer has a layered structure including a first insulating film and a second insulating film arranged on the first insulating film, the second TFT includes a second oxide semiconductor layer having a higher mobility than the first oxide semiconductor layer and a second gate electrode arranged on a part of the second oxide semiconductor layer with a second gate insulating layer interposed therebetween, and the second gate insulating layer includes the second insulating film and does not include the first insulating film, and the second TFT further includes a lower insulating layer including the first insulating film arranged between the second oxide semiconductor layer and a substrate.