公开(公告)号：US06362063B1

公开(公告)日：2002-03-26

申请号：US09226773

申请日：1999-01-06

申请人： Witold P. Maszara ,  Srinath Krishnan ,  Shekhar Pramanick

发明人： Witold P. Maszara ,  Srinath Krishnan ,  Shekhar Pramanick

IPC分类号： H01L21336

CPC分类号： H01L29/66492 ,  H01L21/26506 ,  H01L21/26513

摘要： A shallow abrupt junction is formed in a single crystal substrate, for example, to form a pn junction in a diode or a source drain extension in a transistor. An amorphous layer is formed at the surface of the substrate by implanting an electrically inactive ion, such as germanium or silicon, into the substrate. The amorphous/crystalline interface between the amorphous layer and the base crystal substrate is located at the depth of the desired junction. A dopant species, such as boron, phosphorus or arsenic is implanted into the substrate so that peak concentration of the dopant is at least partially within the amorphous layer. The amorphous layer can be formed either before or after the implanting of the dopant species. A low temperature anneal is used to recrystallize the amorphous layer through solid phase epitaxy, which also activates the dopant within the amorphous layer. The dopant located beneath the original amorphous/crystalline interface remains inactive. Thus, an abrupt junction is formed at the depth of the original amorphous/crystalline interface. Formation of such a shallow abrupt junction is useful in devices such as diodes and transistors, including bipolar, MOSFET and CMOS, and may be used to form source drain extensions and halo regions. Subsequent processing of the substrate has a thermal budget that is approximately equal to or less than the temperature used for the low temperature anneal.

摘要翻译： 在单晶衬底中形成浅的突点，例如在二极管中形成pn结或在晶体管中形成源极漏极延伸。 通过将非活性离子（例如锗或硅）注入到衬底中，在衬底的表面上形成非晶层。 非晶层和基底晶体之间的非晶/晶界面位于所需结的深度处。 掺杂物质如硼，磷或砷被注入到衬底中，使得掺杂剂的峰值浓度至少部分地在非晶层内。 可以在注入掺杂剂物质之前或之后形成非晶层。 低温退火用于通过固相外延重结晶非晶层，这也激活非晶层内的掺杂剂。 位于原始非晶/晶界面之下的掺杂剂保持不活动。 因此，在原始非晶/晶界面的深度处形成突变结。 形成这样一个浅的突变结可用在诸如二极管和晶体管的器件中，包括双极型，MOSFET和CMOS，并且可用于形成源极漏极延伸部分和卤素区域。 衬底的后续处理具有大约等于或小于用于低温退火的温度的热预算。

公开(公告)号：US06288448B1

公开(公告)日：2001-09-11

申请号：US09312208

申请日：1999-05-14

申请人： Shekhar Pramanick

发明人： Shekhar Pramanick

IPC分类号： H01L2348

CPC分类号： H01L21/76834 ,  H01L21/76801 ,  H01L21/76807 ,  H01L23/5226 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor interconnect barrier material of boron silicon nitride is provided for use with copper interconnects. The material is manufactured by a process of combining silane and ammonia in a boron rich atmosphere during a chemical vapor deposition process.

摘要翻译： 提供了一种用于铜互连的氮化硼的半导体互连屏障材料。 该材料通过在化学气相沉积工艺中在富含硼的气氛中组合硅烷和氨的方法制造。

公开(公告)号：US06221724B1

公开(公告)日：2001-04-24

申请号：US09187252

申请日：1998-11-06

申请人： Bin Yu ,  Shekhar Pramanick

发明人： Bin Yu ,  Shekhar Pramanick

IPC分类号： H01L21336

CPC分类号： H01L29/6659 ,  H01L21/26533 ,  H01L21/2658 ,  H01L29/0638 ,  H01L29/0653 ,  H01L29/1083

摘要： An integrated circuit and method of fabrication is provided for an integrated circuit having punch-through suppression. Unlike conventional methods of punch-through suppression wherein a dopant implant is fabricated in the device, the present invention utilizes an inert ion implantation process whereby inert ions are implanted through a fabricated gate structure on the semiconductor substrate to form a region of inert ion implant between source and drain regions of a device on the integrated circuit. This accumulation region prevents punch-through between source and drain regions of the device. In a second embodiment, the inert ion implantation is used in conjunction with the conventional punch-through dopant implant. In this second embodiment, diffusion of the implant during subsequent thermal annealing is suppressed by the inert ion accumulation in the subsurface region of the device. Accordingly, improved integrated circuits and methods of fabricating an integrated circuit having punch-through suppression are disclosed.

摘要翻译： 为具有穿通抑制的集成电路提供集成电路和制造方法。 不同于常规的穿透抑制方法，其中在器件中制造掺杂剂注入，本发明利用惰性离子注入工艺，其中惰性离子通过半导体衬底上制造的栅极结构注入，以形成惰性离子注入区域 集成电路上的器件的源极和漏极区域。 该积聚区域防止器件的源极和漏极区域之间穿透。 在第二实施例中，惰性离子注入与常规穿通掺杂剂注入相结合使用。 在该第二实施例中，通过装置的地下区域中的惰性离子累积来抑制随后的热退火期间的植入物的扩散。 因此，公开了改进的集成电路和制造具有穿通抑制的集成电路的方法。

公开(公告)号：US06214731B1

公开(公告)日：2001-04-10

申请号：US09442771

申请日：1999-11-18

申请人： Takeshi Nogami ,  Minh Van Ngo ,  Shekhar Pramanick

发明人： Takeshi Nogami ,  Minh Van Ngo ,  Shekhar Pramanick

IPC分类号： H01L2144

CPC分类号： H01L21/76856 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76877 ,  H01L23/53233 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： Cu interconnection patterns with improved electromigration resistance are formed by depositing a barrier metal layer, such as W or WN, to line an opening in a dielectric layer. The exposed surface of the deposited barrier metal layer is treated with silane or dichlorosaline to form a thin silicon layer thereon. Cu is then deposited to fill the opening and reacted with the thin silicon layer to form a thin layer of Cu silicide at the interface between Cu and the barrier metal layer, thereby reducing the interface defect density and improving electromigration resistance.

摘要翻译： 具有改善的电迁移电阻的Cu互连图案通过沉积阻挡金属层（例如W或WN）来形成，以对电介质层中的开口进行排列。 沉积的阻挡金属层的暴露表面用硅烷或二氯苯胺处理以在其上形成薄硅层。 然后沉积Cu以填充开口并与薄硅层反应以在Cu和阻挡金属层之间的界面处形成Cu硅化物的薄层，从而降低界面缺陷密度并提高电迁移阻力。

公开(公告)号：US06180469B2

公开(公告)日：2001-01-30

申请号：US09187522

申请日：1998-11-06

申请人： Shekhar Pramanick ,  Qi Xiang ,  Ming-Ren Lin

发明人： Shekhar Pramanick ,  Qi Xiang ,  Ming-Ren Lin

IPC分类号： H01L21336

CPC分类号： H01L29/665 ,  H01L21/28052 ,  H01L21/28518 ,  H01L21/288 ,  H01L21/3215 ,  H01L29/66515

摘要： Low resistivity contacts are formed on source/drain regions and gate electrodes at a suitable thickness to reduce parasitic series resistances, thereby significantly reducing consumption of underlying silicon, while significantly reducing junction leakage. Embodiments include selectively depositing a metal layer, such as nickel, on the source/drain regions and on the gate electrode and ion implanting to form a barrier layer within the nickel layers which does not react with silicon or nickel silicide during subsequent solicitation. The barrier layer confines salicidation to the relatively thin underlayer layer of nickel, thereby minimizing consumption of underlying silicon while the unsilicidized overlying nickel on the barrier layer ensures low sheet resistivity.

摘要翻译： 在源极/漏极区域和栅电极上以合适的厚度形成低电阻率接触以减少寄生串联电阻，从而显着降低底层硅的消耗，同时显着减少结漏电。 实施例包括在源极/漏极区域和栅极上选择性地沉积诸如镍的金属层和离子注入，以在镍层内形成阻挡层，其在随后的引诱期间不与硅或硅化镍反应。 阻挡层限制了相对薄的镍底层的盐析，从而最小化下层硅的消耗，而阻挡层上的无硅覆盖的镍确保了低的电阻率。

公开(公告)号：US06172421B2

公开(公告)日：2001-01-09

申请号：US09132282

申请日：1998-08-11

申请人： Paul Raymond Besser ,  Shekhar Pramanick ,  Takeshi Nogami ,  Subhash Gupta

发明人： Paul Raymond Besser ,  Shekhar Pramanick ,  Takeshi Nogami ,  Subhash Gupta

IPC分类号： H01L2348

CPC分类号： H01L21/76858 ,  H01L21/76849 ,  H01L21/76886

摘要： The present invention relates to the formation of a protective intermetallic layer 15 on the surface of damascene metal interconnects 12 during semiconductor fabrication. The intermetallic layer 15 prevents problems associated with formation of an oxide layer on the surface of the interconnect. The intermetallic layer is formed by depositing a metal on the surface of the interconnect that will both reduce any present metal oxide layer and form an intermetallic with the interconnect metal.

摘要翻译： 本发明涉及在半导体制造期间在镶嵌金属互连件12的表面上形成保护性金属间化合物层15。 金属间层15防止与互连表面上形成氧化物层有关的问题。 金属间化合物层通过在互连表面上沉积金属而形成，该金属将既减少任何存在的金属氧化物层并与互连金属形成金属间化合物。

公开(公告)号：US6165894A

公开(公告)日：2000-12-26

申请号：US131872

申请日：1998-08-10

申请人： Shekhar Pramanick ,  Takeshi Nogami ,  Minh Van Ngo

发明人： Shekhar Pramanick ,  Takeshi Nogami ,  Minh Van Ngo

IPC分类号： H01L21/768 ,  H01L23/532 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC分类号： H01L21/76886 ,  H01L21/76834 ,  H01L21/76862 ,  H01L21/76877 ,  H01L23/53233 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： The adhesion of a diffusion barrier or capping layer to a Cu or Cu alloy interconnect member is significantly enhanced by treating the exposed surface of the Cu or Cu alloy interconnect member with an ammonia plasma followed by depositing the diffusion barrier layer on the treated surface. Embodiments include electroplating or electroless plating Cu or a Cu alloy to fill a damascene opening in a dielectric interlayer, chemical mechanical polishing, treating the exposed surface of the Cu/Cu alloy interconnect with an ammonia plasma, and depositing a silicon nitride diffusion barrier layer directly on the plasma treated surface.

摘要翻译： 通过用氨等离子体处理Cu或Cu合金互连构件的暴露表面，然后在经处理的表面上沉积扩散阻挡层，扩散阻挡层或覆盖层对Cu或Cu合金互连构件的粘附性显着增强。 实施例包括电镀或化学镀Cu或Cu合金以填充介电中间层中的镶嵌开口，化学机械抛光，用氨等离子体处理Cu / Cu合金互连的暴露表面，并直接沉积氮化硅扩散阻挡层 在等离子体处理的表面上。

公开(公告)号：US6147000A

公开(公告)日：2000-11-14

申请号：US225546

申请日：1999-01-05

申请人： Lu You ,  Shekhar Pramanick ,  Takeshi Nogami

发明人： Lu You ,  Shekhar Pramanick ,  Takeshi Nogami

IPC分类号： H01L21/768 ,  H01L21/44 ,  H01L21/4763

CPC分类号： H01L21/76886 ,  H01L21/76849 ,  H01L21/76858

摘要： A Cu interconnect member is passivated by diffusing Sn, Ta or Cr atoms into its upper surface to form an intermetallic layer. Embodiments include depositing Cu by electroplating or electroless plating to fill a damascene opening in a dielectric layer, CMP, depositing a sacrificial layer of Sn, Ta or Cr on the planarized surface, heating to diffuse Sn, Ta or Cr into the upper surface of the deposited Cu to form a passivating intermetallic alloy layer, and removing any remaining sacrificial layer by CMP or etching.

摘要翻译： 通过将Sn，Ta或Cr原子扩散到其上表面来形成金属间化合物来钝化Cu互连构件。 实施例包括通过电镀或化学电镀沉积Cu以填充电介质层中的镶嵌开口，CMP，在平坦化表面上沉积Sn，Ta或Cr的牺牲层，加热以将Sn，Ta或Cr扩散到 沉积Cu以形成钝化金属间合金层，并通过CMP或蚀刻去除任何残留的牺牲层。

公开(公告)号：US06144099A

公开(公告)日：2000-11-07

申请号：US282079

申请日：1999-03-30

申请人： Sergey D. Lopatin ,  Shekhar Pramanick ,  Dirk Brown

发明人： Sergey D. Lopatin ,  Shekhar Pramanick ,  Dirk Brown

IPC分类号： H01L21/288 ,  H01L21/768 ,  H01L23/485 ,  H01L23/532 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L21/76846 ,  H01L21/288 ,  H01L21/76849 ,  H01L23/485 ,  H01L23/53238 ,  H01L2924/0002

摘要： A semiconductor metalization barrier, and manufacturing method therefor, is provided which is a stack of a cobalt layer and cobalt tungsten layer deposited on a copper bonding pad.

摘要翻译： 提供了一种半导体金属化屏障及其制造方法，其是沉积在铜焊盘上的钴层和钴钨层的堆叠。

公开(公告)号：US6074937A

公开(公告)日：2000-06-13

申请号：US58897

申请日：1998-04-13

申请人： Shekhar Pramanick ,  Che-Hoo Ng ,  Emi Ishida

发明人： Shekhar Pramanick ,  Che-Hoo Ng ,  Emi Ishida

IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L21/425

CPC分类号： H01L29/6659 ,  H01L21/26506 ,  H01L21/2652

摘要： Lightly doped regions are implanted into an amorphous region in the semiconductor substrate to significantly reduce transient enhanced diffusion upon subsequent activation annealing. A sub-surface non-amorphous region is also formed before activation annealing to substantially eliminate end-of-range defects on crystallization of amorphous region containing the lightly doped implants.

摘要翻译： 将轻掺杂区域注入到半导体衬底中的非晶区域中，以在随后的激活退火时显着减少瞬时增强的扩散。 在激活退火之前还形成亚表面非非晶区域，以基本上消除含有轻掺杂植入物的非晶区域的结晶范围内的范围内缺陷。