公开(公告)号：US06967160B1

公开(公告)日：2005-11-22

申请号：US11042194

申请日：2005-01-26

申请人： Eric Paton ,  Paul Raymond Besser ,  Simon S. Chan ,  Fred Hause

发明人： Eric Paton ,  Paul Raymond Besser ,  Simon S. Chan ,  Fred Hause

IPC分类号： H01L21/28 ,  H01L21/00 ,  H01L21/265 ,  H01L21/285 ,  H01L21/336 ,  H01L21/44 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L29/78 ,  H01L29/786

CPC分类号： H01L21/28518 ,  H01L21/26506 ,  H01L21/28052 ,  H01L29/665 ,  H01L29/6659

摘要： Nickel silicide formation with significantly reduced interface roughness is achieved by forming a diffusion modulating layer between the underlying silicon and nickel silicide layers. Embodiments include ion implanting nitrogen into the substrate and gate electrode, depositing a thin layer of titanium or tantalum, depositing a layer of nickel, and then heating to form a diffusion modulating layer containing nitrogen at the interface between the underlying silicon and nickel silicide layers.

摘要翻译： 通过在下面的硅和硅化镍层之间形成扩散转换层来实现具有显着降低的界面粗糙度的硅化镍形成。 实施例包括将氮离子注入到衬底和栅电极中，沉积钛或钽的薄层，沉积镍层，然后加热以形成在下硅和硅化镍层之间的界面处含有氮的扩散调制层。

公开(公告)号：US06897144B1

公开(公告)日：2005-05-24

申请号：US10100915

申请日：2002-03-20

申请人： Minh Van Ngo ,  Paul Raymond Besser ,  Larry Zhao

发明人： Minh Van Ngo ,  Paul Raymond Besser ,  Larry Zhao

IPC分类号： H01L21/4763 ,  H01L21/768

CPC分类号： H01L21/76834 ,  H01L21/76877

摘要： The electromigration resistance of nitride capped Cu lines is significantly improved by controlling the nitride deposition conditions to reduce the compressive stress of the deposited nitride layer, thereby reducing diffusion along the Cu-nitride interface. Embodiments include depositing a silicon nitride capping layer on inlaid Cu using dual frequency powers, holding the high frequency power constant and controlling the compressive stress of the deposited silicon nitride capping layer by varying the low frequency power to the susceptor, thereby enabling reduction of the compressive stress below about 2×107 Pascals. Embodiments also include sequentially and contiguously treating the exposed planarized surface of in-laid Cu with a soft plasma containing NH3 diluted with N2, and then depositing the silicon nitride capping layer by plasma enhanced chemical vapor deposition, while varying the low frequency power between about 100 to about 300 watts. Embodiments also include Cu dual damascene structures formed in dielectric material having a dielectric constant (k) less than about 3.9.

摘要翻译： 通过控制氮化物沉积条件以减小沉积的氮化物层的压应力，从而减少沿着Cu-氮化物界面的扩散，显着改善了氮化物覆盖的Cu线的电迁移电阻。 实施例包括使用双频功率在镶嵌Cu上沉积氮化硅覆盖层，保持高频功率恒定，并通过改变对基座的低频功率来控制沉积的氮化硅覆盖层的压缩应力，从而能够降低压缩 压力低于约2×10 7帕斯卡。 实施例还包括用含N 2 N 3稀释的含有NH 3的软质等离子体连续地并且连续地处理暴露的在内的Cu的平坦化表面，然后沉积氮化硅覆盖层 通过等离子体增强化学气相沉积，同时改变约100至约300瓦特之间的低频功率。 实施例还包括形成在介电常数（k）小于约3.9的电介质材料中的Cu双镶嵌结构。

公开(公告)号：US06689688B2

公开(公告)日：2004-02-10

申请号：US10180858

申请日：2002-06-25

申请人： Paul Raymond Besser ,  Simon S. Chan ,  David E. Brown ,  Eric Paton

发明人： Paul Raymond Besser ,  Simon S. Chan ,  David E. Brown ,  Eric Paton

IPC分类号： H01L2144

CPC分类号： H01L21/28518

摘要： A method for forming silicide contacts includes forming a layer on silicon-containing active device regions such as source, drain, and gate regions. The layer contains a metal that is capable of forming one or more metal silicides and a material that is soluble in a first metal silicide but not soluble in a second metal silicide, or is more soluble in the first metal silicide than in the second metal silicide. The layer may be formed by vapor deposition methods such as physical vapor deposition, chemical vapor deposition, evaporation, laser ablation, or other deposition method. A method for forming silicide contacts includes forming a metal layer, then implanting the metal layer and/or underlying silicon layer with a material such as that described above. The material may be implanted in the silicon layer prior to formation of the metal layer. Contacts formed include a first metal silicide and a material that is more soluble in a first metal silicide than in a second metal silicide. The contacts may be part of a semiconductor device including a substrate, active region containing silicon, and silicide contacts disposed over the active region and capable of electrically coupling the active region to other regions such as metallization lines.

摘要翻译： 用于形成硅化物接触的方法包括在诸如源极，漏极和栅极区域的含硅有源器件区域上形成层。 该层包含能够形成一种或多种金属硅化物的金属和可溶于第一金属硅化物但不溶于第二金属硅化物的材料，或者比第二金属硅化物更可溶于第一金属硅化物 。 该层可以通过诸如物理气相沉积，化学气相沉积，蒸发，激光烧蚀或其它沉积方法之类的气相沉积方法形成。 形成硅化物接触的方法包括形成金属层，然后用如上所述的材料注入金属层和/或下层硅层。 在形成金属层之前，材料可以被植入到硅层中。 形成的触点包括第一金属硅化物和在第一金属硅化物中比在第二金属硅化物中更可溶的材料。 触点可以是半导体器件的一部分，其包括衬底，含硅的有源区和设置在有源区上的硅化物触点，并且能够将有源区电耦合到诸如金属化线的其它区域。

公开(公告)号：US06429128B1

公开(公告)日：2002-08-06

申请号：US09902587

申请日：2001-07-12

申请人： Paul Raymond Besser ,  Minh Van Ngo ,  Larry Zhao

发明人： Paul Raymond Besser ,  Minh Van Ngo ,  Larry Zhao

IPC分类号： H01L2144

CPC分类号： H01L21/76862 ,  H01L21/3185 ,  H01L21/76834 ,  H01L21/76883 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： The electromigration resistance of nitride capped Cu lines is significantly improved by controlling the nitride deposition conditions to reduce the compressive stress of the deposited nitride layer, thereby reducing diffusion along the Cu-nitride interface. Embodiments include depositing a silicon nitride capping layer on inlaid Cu at a reduced RF power, e.g., about 400 to about 500 watts and an increased spacing, e.g., about 680 to about 720 mils, to reduce the compressive stress of the deposited silicon nitride layer to below about 2×107 Pascals. Embodiments also include sequentially and contiguously treating the exposed planarized surface of in-laid Cu with a soft plasma containing NH3 diluted with N2, ramping up the introduction of SiH4 and then initiating plasma enhanced chemical vapor deposition of a silicon nitride capping layer, while maintaining substantially the same pressure and N2 flow rate during plasma treatment, SiH4 ramp up and silicon nitride deposition. Embodiments also include Cu dual damascene structures formed in dielectric material having a dielectric constant (k) less than about 3.9.

摘要翻译： 通过控制氮化物沉积条件以减小沉积的氮化物层的压应力，从而减少沿着Cu-氮化物界面的扩散，显着改善了氮化物覆盖的Cu线的电迁移电阻。 实施例包括以降低的RF功率（例如，约400至约500瓦特）和增加的间隔（例如，约680至约720密耳）在镶嵌的Cu上沉积氮化硅覆盖层，以减小沉积的氮化硅层的压应力 低于约2×107帕斯卡。 实施例还包括用包含用N 2稀释的NH 3的软质等离子体连续和连续地处理嵌入的Cu的暴露的平坦化表面，使引入SiH4升高，然后启动氮化硅覆盖层的等离子体增强化学气相沉积，同时保持基本上 在等离子体处理期间，相同的压力和N2的流速，SiH4斜坡上升和氮化硅沉积。 实施例还包括形成在介电常数（k）小于约3.9的电介质材料中的Cu双镶嵌结构。

公开(公告)号：US6162689A

公开(公告)日：2000-12-19

申请号：US187231

申请日：1998-11-06

申请人： Nick Kepler ,  Karsten Wieczorek ,  Larry Wang ,  Paul Raymond Besser

发明人： Nick Kepler ,  Karsten Wieczorek ,  Larry Wang ,  Paul Raymond Besser

IPC分类号： H01L21/266 ,  H01L21/285 ,  H01L21/336 ,  H01L29/417

CPC分类号： H01L29/66598 ,  H01L21/266 ,  H01L21/28518 ,  H01L29/41775 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659

摘要： High integrity ultra-shallow source/drain junctions are formed employing cobalt silicide contacts. Emdodiments include forming field oxide regions, gates, spacers, and lightly doped implants, and then depositing a layer of oxide on a substrate. The oxide layer is masked to protect portions of the oxide layer located near the gate, where it is desired to have a shallow junction, then etched to expose portions of the intended source/drain regions where the silicided contacts are to be formed. A high-dosage source/drain implant is thereafter carried out to form deep source/drain junctions with the substrate where the oxide layer has been etched away, and to form shallower junctions near the gates, where the implant must travel through the oxide layer before reaching the substrate. A layer of cobalt is thereafter deposited and silicidation is performed to form metal silicide contacts over only the deep source/drain junctions, while the cobalt on the oxide layer (i.e., above the shallower junctions) does not react to form cobalt silicide, and is thereafter removed. The present invention provides ultra-shallow source-drain junctions near the gates for improved electrical characteristics, and deeper junctions away from the gates, with cobalt silicide contacts above only the deeper junction portions to avoid junction leakage, thereby facilitating reliable device scaling.

摘要翻译： 使用硅化钴接触形成高完整性超浅源极/漏极结。 实例包括形成场氧化物区域，栅极，间隔物和轻掺杂的植入物，然后在衬底上沉积氧化物层。 掩模氧化层以保护位于栅极附近的氧化物层的部分，期望具有浅结，然后蚀刻以暴露要形成硅化物触点的预期源/漏区的部分。 此后，进行高剂量源/漏注入，以与氧化物层被蚀刻掉的衬底形成深的源极/漏极结，并且在栅极附近形成较浅的结，其中植入物必须在 到达基板。 此后沉积一层钴，并且仅在深源极/漏极接合处进行硅化以形成金属硅化物接触，而氧化物层上的钴（即，较浅的接合点上方）不反应形成硅化钴，并且是 此后取出。 本发明提供了栅极附近的超浅源极 - 漏极结，用于改善电气特性，以及远离栅极的较深的结，钴硅化物接触仅在较深的接合部分上方，以避免结漏电，从而便于可靠的器件缩放。

公开(公告)号：US6096599A

公开(公告)日：2000-08-01

申请号：US187521

申请日：1998-11-06

申请人： Nick Kepler ,  Karsten Wieczorek ,  Larry Wang ,  Paul Raymond Besser

发明人： Nick Kepler ,  Karsten Wieczorek ,  Larry Wang ,  Paul Raymond Besser

IPC分类号： H01L21/225 ,  H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/8242

CPC分类号： H01L29/66575 ,  H01L21/2257 ,  H01L21/28052 ,  H01L21/28518 ,  H01L21/823814 ,  H01L21/823835 ,  H01L29/665 ,  Y10S438/923

摘要： High integrity shallow source/drain junctions are formed employing cobalt silicide contacts. Embodiments include depositing a layer of cobalt on a substrate above intended source/drain regions, depositing a cap layer of titanium or titanium nitride on the cobalt, depositing a doped film on the cap layer, and performing silicidation, as by rapid thermal annealing, to form a low-resistivity cobalt silicide and to diffuse impurities from the doped film through the cobalt silicide into the substrate to form a junction extending into the substrate a constant depth below the cobalt silicide interface. The formation of source/drain junctions self-aligned to the cobalt silicide/silicon interface prevents junction leakage while allowing the formation of cobalt silicide contacts at optimum thickness, thereby facilitating reliable device scaling.

摘要翻译： 使用硅化钴接触形成高度完整的浅源极/漏极结。 实施例包括在目标源极/漏极区域上的衬底上沉积钴层，在钴上沉积钛或氮化钛的覆盖层，在覆盖层上沉积掺杂的膜，并通过快速热退火进行硅化， 形成低电阻率的硅化钴，并且通过硅化钴将掺杂的膜中的杂质扩散到衬底中，以形成在硅化钴界面下面延伸到衬底中的恒定深度的结。 与硅化钴/硅界面自对准的源极/漏极结的形成防止结漏，同时允许在最佳厚度下形成硅化钴触点，从而便于可靠的器件缩放。

公开(公告)号：US07309650B1

公开(公告)日：2007-12-18

申请号：US11065388

申请日：2005-02-24

申请人： Connie Pin-Chin Wang ,  Lu You ,  Zoran Krivokapic ,  Paul Raymond Besser ,  Suzette Keefe Pangrle

发明人： Connie Pin-Chin Wang ,  Lu You ,  Zoran Krivokapic ,  Paul Raymond Besser ,  Suzette Keefe Pangrle

IPC分类号： H01L21/44

CPC分类号： H01L29/7833 ,  B82Y10/00 ,  H01L21/28273 ,  H01L29/42332

摘要： A memory device having a metal nanocrystal charge storage structure and a method for its manufacture. The memory device may be manufactured by forming a first oxide layer on the semiconductor substrate, then disposing a porous dielectric layer on the oxide layer and disposing a second oxide layer on the porous dielectric layer. A layer of electrically conductive material is formed on the second layer of dielectric material. An etch mask is formed on the electrically conductive material. The electrically conductive material and the underlying dielectric layers are anisotropically etched to form a dielectric structure on which a gate electrode is disposed. A metal layer is formed on the dielectric structure and the gate electrode and treated so that portions of the metal layer diffuse into the porous dielectric layer. Then the metal layer is removed.

摘要翻译： 一种具有金属纳米晶体电荷存储结构的存储器件及其制造方法。 存储器件可以通过在半导体衬底上形成第一氧化物层，然后在氧化物层上设置多孔介电层并在第二氧化物层上设置第二氧化物层来制造。 在第二介电材料层上形成一层导电材料。 在导电材料上形成蚀刻掩模。 导电材料和下面的介电层被各向异性地蚀刻以形成其上设置有栅电极的电介质结构。 在介电结构和栅电极上形成金属层，并处理金属层的一部分扩散到多孔介电层中。 然后去除金属层。

公开(公告)号：US07476604B1

公开(公告)日：2009-01-13

申请号：US11128391

申请日：2005-05-13

申请人： Ning Cheng ,  Minh Van Ngo ,  Jinsong Yin ,  Paul Raymond Besser ,  Connie Pin-chin Wang ,  Russell Rosaire Austin Callahan ,  Jeffrey Shields ,  Shankar Sinha ,  Jeff P. Erhardt ,  Jeremy Chi-Hung Chou

发明人： Ning Cheng ,  Minh Van Ngo ,  Jinsong Yin ,  Paul Raymond Besser ,  Connie Pin-chin Wang ,  Russell Rosaire Austin Callahan ,  Jeffrey Shields ,  Shankar Sinha ,  Jeff P. Erhardt ,  Jeremy Chi-Hung Chou

IPC分类号： H01L21/44

CPC分类号： H01L21/76831 ,  H01L21/02063 ,  H01L21/28518 ,  H01L21/76814 ,  H01L21/76843 ,  H01L21/76855

摘要： A method of forming a contact through a material includes forming a via through a dielectric material and cleaning the via using a dilute hydrofluoric (DHF) acid solution. The method further includes depositing a barrier layer within the via and depositing metal adjacent the barrier layer.

摘要翻译： 通过材料形成接触的方法包括通过电介质材料形成通孔，并使用稀氢氟酸（DHF）酸溶液清洗通孔。 所述方法还包括在所述通孔内沉积阻挡层并在所述阻挡层附近沉积金属。

公开(公告)号：US07319065B1

公开(公告)日：2008-01-15

申请号：US10637406

申请日：2003-08-08

申请人： Wen Yu ,  Paul Raymond Besser

发明人： Wen Yu ,  Paul Raymond Besser

IPC分类号： H01L21/4763

CPC分类号： H01L21/76816 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor component having a composite via structure with an enhanced aspect ratio and a method for manufacturing the semiconductor component. Vias having a first aspect ratio are formed in a contact layer disposed on a semiconductor substrate and filled with a metal. The metal is planarized and a dielectric layer is formed over the contact layer. Via extension structures having the same aspect ratio as those in the contact layer are formed in the dielectric layer and aligned with the vias in the contact layer. The vias in the dielectric layer are filled with metal and the metal is planarized. The contact vias in the contact layer and the dielectric layer cooperate to form a composite via structure having the enhanced aspect ratio. Additional dielectric layers having via structures can be included in the composite contact structure to further enhance the aspect ratio of the via structure.

摘要翻译： 具有增强纵横比的复合通孔结构的半导体部件和半导体部件的制造方法。 具有第一纵横比的通孔形成在设置在半导体衬底上并被金属填充的接触层中。 金属被平坦化，并且在接触层上形成电介质层。 在电介质层中形成具有与接触层相同的纵横比的延伸结构，并与接触层中的通孔对准。 电介质层中的通孔用金属填充，金属被平坦化。 接触层和电介质层中的接触孔合作形成具有增强的纵横比的复合通孔结构。 具有通孔结构的附加电介质层可以包括在复合接触结构中，以进一步增强通孔结构的纵横比。

公开(公告)号：US6110829A

公开(公告)日：2000-08-29

申请号：US956343

申请日：1997-10-23

申请人： Paul Raymond Besser ,  Robin W. Cheung ,  Guarionex Morales

发明人： Paul Raymond Besser ,  Robin W. Cheung ,  Guarionex Morales

IPC分类号： H01L21/768 ,  H01L23/532 ,  H01L21/44

CPC分类号： H01L21/76882 ,  H01L21/76877 ,  H01L23/53219 ,  H01L2924/0002 ,  Y10S148/058 ,  Y10S420/903

摘要： An aluminum fill process for sub-0.25 .mu.m technology integrated circuits that has a reflow temperature less than 400.degree. C. that has low alloy resistivity and excellent electromigration characteristics. The aluminum allow is composed of Al-1% Ge-1% Cu.

摘要翻译： 铝合金填充工艺为0.25微米以下的技术集成电路，其回流温度低于400℃，具有低合金电阻率和优异的电迁移特性。 铝允许由Al-1％Ge-1％Cu组成。