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    Method of forming a MOSFET transistor with a shallow abrupt retrograde dopant profile
    1.
    发明授权
    Method of forming a MOSFET transistor with a shallow abrupt retrograde dopant profile 有权
    形成具有浅突变逆向掺杂剂分布的MOSFET晶体管的方法

    公开(公告)号：US06184112B2

    公开(公告)日：2001-02-06

    申请号：US09204998

    申请日：1998-12-02

    申请人： Witold P. Maszara ,  Srinath Krishnan ,  Shekhar Pramanick

    发明人： Witold P. Maszara ,  Srinath Krishnan ,  Shekhar Pramanick

    IPC分类号： H01L21425

    CPC分类号： H01L21/26513 ,  H01L21/26506 ,  H01L29/105 ,  H01L29/66545

    摘要： In accordance with the present invention, an amorphous layer is formed in a crystalline substrate (e.g., the channel region of a MOSFET transistor) by, for example, implanting ions of an inert specie such as germanium. A dopant is implanted so that it overlaps with the amorphous layer. Subsequently, low temperature recrystallization of the amorphous layer leads to an abrupt retrograded layer of active dopant in the channel region of the MOSFET. This retrograded dopant layer could be formed before or after the formation of the gate electrode.

    摘要翻译： 根据本发明，通过例如注入诸如锗的惰性物质的离子，在晶体衬底（例如，MOSFET晶体管的沟道区）中形成非晶层。 注入掺杂剂使其与非晶层重叠。 随后，非晶层的低温重结晶导致在MOSFET的沟道区域中的有源掺杂剂的突然退化层。 可以在形成栅电极之前或之后形成该退化的掺杂剂层。

    Formation of low thermal budget shallow abrupt junctions for semiconductor devices
    2.
    发明授权
    Formation of low thermal budget shallow abrupt junctions for semiconductor devices 有权
    形成半导体器件低热预算浅突点

    公开(公告)号：US06362063B1

    公开(公告)日：2002-03-26

    申请号：US09226773

    申请日：1999-01-06

    申请人： Witold P. Maszara ,  Srinath Krishnan ,  Shekhar Pramanick

    发明人： Witold P. Maszara ,  Srinath Krishnan ,  Shekhar Pramanick

    IPC分类号： H01L21336

    CPC分类号： H01L29/66492 ,  H01L21/26506 ,  H01L21/26513

    摘要： A shallow abrupt junction is formed in a single crystal substrate, for example, to form a pn junction in a diode or a source drain extension in a transistor. An amorphous layer is formed at the surface of the substrate by implanting an electrically inactive ion, such as germanium or silicon, into the substrate. The amorphous/crystalline interface between the amorphous layer and the base crystal substrate is located at the depth of the desired junction. A dopant species, such as boron, phosphorus or arsenic is implanted into the substrate so that peak concentration of the dopant is at least partially within the amorphous layer. The amorphous layer can be formed either before or after the implanting of the dopant species. A low temperature anneal is used to recrystallize the amorphous layer through solid phase epitaxy, which also activates the dopant within the amorphous layer. The dopant located beneath the original amorphous/crystalline interface remains inactive. Thus, an abrupt junction is formed at the depth of the original amorphous/crystalline interface. Formation of such a shallow abrupt junction is useful in devices such as diodes and transistors, including bipolar, MOSFET and CMOS, and may be used to form source drain extensions and halo regions. Subsequent processing of the substrate has a thermal budget that is approximately equal to or less than the temperature used for the low temperature anneal.

    摘要翻译： 在单晶衬底中形成浅的突点，例如在二极管中形成pn结或在晶体管中形成源极漏极延伸。 通过将非活性离子（例如锗或硅）注入到衬底中，在衬底的表面上形成非晶层。 非晶层和基底晶体之间的非晶/晶界面位于所需结的深度处。 掺杂物质如硼，磷或砷被注入到衬底中，使得掺杂剂的峰值浓度至少部分地在非晶层内。 可以在注入掺杂剂物质之前或之后形成非晶层。 低温退火用于通过固相外延重结晶非晶层，这也激活非晶层内的掺杂剂。 位于原始非晶/晶界面之下的掺杂剂保持不活动。 因此，在原始非晶/晶界面的深度处形成突变结。 形成这样一个浅的突变结可用在诸如二极管和晶体管的器件中，包括双极型，MOSFET和CMOS，并且可用于形成源极漏极延伸部分和卤素区域。 衬底的后续处理具有大约等于或小于用于低温退火的温度的热预算。

    Method of manufacturing a transistor with local insulator structure
    3.
    发明授权
    Method of manufacturing a transistor with local insulator structure 有权
    制造具有局部绝缘体结构的晶体管的方法

    公开(公告)号：US06380019B1

    公开(公告)日：2002-04-30

    申请号：US09187498

    申请日：1998-11-06

    申请人： Bin Yu ,  Ming-Ren Lin ,  Shekhar Pramanick

    发明人： Bin Yu ,  Ming-Ren Lin ,  Shekhar Pramanick

    IPC分类号： H01L2976

    CPC分类号： H01L21/74 ,  H01L29/0649 ,  H01L29/6659

    摘要： A thin filmed fully-depleted silicon-on-insulator (SOI) metal oxide semiconductor field effect transistor (MOSFET) utilizes a local insulation structure. The local insulative structure includes a buried silicon dioxide region under the channel region. The MOSFET body thickness is very small and yet silicon available outside of the channel region and buried silicon dioxide region is available for sufficient depths of silicide in the source and drain regions. The buried silicon dioxide region can be formed by a trench isolation technique or a LOCOS technique.

    摘要翻译： 薄膜完全耗尽的绝缘体上硅（SOI）金属氧化物半导体场效应晶体管（MOSFET）利用局部绝缘结构。 局部绝缘结构包括沟道区下方的埋置二氧化硅区域。 MOSFET体的厚度非常小，而在沟道区域和掩埋的二氧化硅区域之外可用的硅可用于源极和漏极区域中足够的硅化物深度。 掩埋的二氧化硅区域可以通过沟槽隔离技术或LOCOS技术形成。

    Chemical-mechanical polishing of semiconductors
    4.
    发明授权
    Chemical-mechanical polishing of semiconductors 有权
    半导体化学机械抛光

    公开(公告)号：US06350678B1

    公开(公告)日：2002-02-26

    申请号：US09534906

    申请日：2000-03-23

    申请人： Shekhar Pramanick ,  Kai Yang

    发明人： Shekhar Pramanick ,  Kai Yang

    IPC分类号： H01L214763

    CPC分类号： H01L21/3212 ,  H01L21/7684

    摘要： A method for manufacturing an integrated circuit using damascene processes is provided in which planar surfaces of contacting conductive metal channels and vias are subjected to chemical-mechanical polishing under a pressure which avoids cold working and to two steps of chemical-mechanical polishing in which the first step is performed using a slurry with a first sized abrasive to expose a first dielectric layer in which the conductive metal channel is embedded and to provide a planar polished surface of the conductive material, and a second step is performed using a second slurry with a second sized abrasive larger than said first sized abrasive to provide a planar rough-polished surface of the conductive material. The second polishing also performed at a pressure which avoids cold working, which causes a highly polycrystalline structure and a high dislocation density, in the conductive material at its planar polished surface.

    摘要翻译： 提供一种使用镶嵌工艺制造集成电路的方法，其中接触导电金属通道和通孔的平坦表面在避免冷加工的压力下进行化学机械抛光，并进行两步化学机械抛光，其中第一 使用具有第一尺寸磨料的浆料进行步骤以暴露其中嵌入有导电金属通道的第一介电层，并提供导电材料的平面抛光表面，并且使用第二浆料进行第二步骤 大于所述第一尺寸磨料的磨料，以提供导电材料的平面粗糙抛光表面。 第二次抛光也在避免冷加工的压力下进行，这导致在其平面抛光表面的导电材料中导致高度多晶结构和高位错密度。

    Self-aligned silicide gate technology for advanced deep submicron MOS device
    5.
    发明授权
    Self-aligned silicide gate technology for advanced deep submicron MOS device 有权
    用于先进深亚微米MOS器件的自对准硅化物栅极技术

    公开(公告)号：US06239452B1

    公开(公告)日：2001-05-29

    申请号：US09320682

    申请日：1999-05-27

    申请人： Qi Xiang ,  Shekhar Pramanick ,  Ming-Ren Lin

    发明人： Qi Xiang ,  Shekhar Pramanick ,  Ming-Ren Lin

    IPC分类号： H01L2184

    CPC分类号： H01L29/6659 ,  H01L21/28097 ,  H01L29/456 ,  H01L29/4975 ,  H01L29/665

    摘要： A deep submicron MOS device having a self-aligned silicide gate structure and a method for forming the same is provided so as to overcome the problems of poly-Si depletion and boron penetration. A first Nickel silicide layer is formed between a gate oxide and a polycrystalline silicon gate electrode. Further, second Nickel silicide layers are formed over highly-doped source/drain regions. In this fashion, the reliability of the MOS device will be enhanced.

    摘要翻译： 提供了具有自对准硅化物栅极结构的深亚微米MOS器件及其形成方法，以克服多Si耗尽和硼渗透的问题。 在栅极氧化物和多晶硅栅电极之间形成第一镍硅化物层。 此外，第二镍硅化物层形成在高掺杂源/漏区上。 以这种方式，MOS器件的可靠性将得到提高。

    Formation of low resistance, ultra shallow LDD junctions employing a sub-surface, non-amorphous implant
    8.
    发明授权
    Formation of low resistance, ultra shallow LDD junctions employing a sub-surface, non-amorphous implant 失效
    形成低电阻，超浅LDD结，采用子表面非非晶态植入物

    公开(公告)号：US6087209A

    公开(公告)日：2000-07-11

    申请号：US126775

    申请日：1998-07-31

    申请人： Geoffrey Choh-Fei Yeap ,  Akif Sultan ,  Shekhar Pramanick

    发明人： Geoffrey Choh-Fei Yeap ,  Akif Sultan ,  Shekhar Pramanick

    IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L29/10

    CPC分类号： H01L29/6659 ,  H01L21/26506 ,  H01L21/26513 ,  H01L29/1079 ,  Y10S148/053

    摘要： Ultra shallow, low resistance LDD junctions are achieved by forming an LDD implant generating an interstitial-rich section and forming a sub-surface, non-amorphous region generating a vacancy-rich region substantially overlapping the interstitial rich region generated when forming the LDD implant. Embodiments include ion implanting, Ge or Si to form surface amorphous and sub-surface, non-amorphous regions, and implanting B or BF.sub.2 to form the impurity region. Embodiments include forming the sub-surface, non-amorphous region before or after generating the surface amorphous region, and forming the impurity region before or after forming the sub-surface, non-amorphous region but after forming the surface amorphous region.

    摘要翻译： 通过形成LDD注入产生富含间隙的部分并形成基本上与形成LDD植入物时产生的间隙富集区域重叠的空位丰富区域的亚表面非非晶区域来实现超浅，低电阻LDD结。 实施例包括离子注入，Ge或Si以形成表面无定形和亚表面非非晶区域，以及注入B或BF 2以形成杂质区域。 实施例包括在产生表面无定形区域之前或之后形成子表面非非晶区域，以及在形成子表面非非晶区域之后或在形成表面无定形区域之后形成杂质区域。

    Semiconductor interconnect barrier for fluorinated dielectrics
    9.
    发明授权
    Semiconductor interconnect barrier for fluorinated dielectrics 有权
    用于氟化电介质的半导体互连屏障

    公开(公告)号：US6054398A

    公开(公告)日：2000-04-25

    申请号：US311735

    申请日：1999-05-14

    申请人： Shekhar Pramanick

    发明人： Shekhar Pramanick

    IPC分类号： H01L21/768 ,  H01L24/48

    CPC分类号： H01L21/76846 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76841 ,  H01L21/76843

    摘要： A method is provided for forming tantalum adhesion/barrier layers on semiconductor channels or in vias in low dielectric constant, fluorinated dielectric layers. The dielectric layers are defluorinated using hydrogen, ammonia, methane, or silane plasma and a subsequent tantalum deposition forms a less fluorine reactive tantalum carbide or tantalum silicide. Tantalum or tantalum nitride is then deposited over the less reactive form of tantalum to form the adhesion/barrier for deposition of a subsequent seed layer and a conductive material to form the vias and channels.

    摘要翻译： 提供了一种用于在半导体通道上或在低介电常数氟化电介质层中的通路中形成钽粘附/阻挡层的方法。 使用氢，氨，甲烷或硅烷等离子体对介电层进行氟化，随后的钽沉积形成较少的氟反应性碳化钽或硅化钽。 然后将钽或氮化钽沉积在较不反应形式的钽上以形成用于沉积后续种子层和导电材料以形成通孔和通道的粘附/屏障。