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31.发明授权公开(公告)号：US10008170B2
公开(公告)日：2018-06-26
申请号：US14905879
申请日：2015-12-30
Inventor： Xiaoxiao Wang , Peng Du
IPC: G09G3/36
CPC classification number: G09G3/3677 , G09G3/3696 , G09G2300/0809 , G09G2310/0286 , G11C19/28
Abstract: The present invention proposes a GOA circuit and a display device adopting the same. The GOA circuit includes thirteen transistors and a first capacitor. The GOA circuit can be driven in 2D and 3D driving modes to prolong charging time of each pixel. Each two GOA circuit units share a set of Nth stage start pulse signals, Nth stage gate pulse signals and eight clock pulse signals. Because the charging time of each pixel is prolonged, the display device can show images with better display quality.
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公开(公告)号：US09893096B2
公开(公告)日：2018-02-13
申请号：US14760750
申请日：2015-06-17
Applicant: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD. , WUHAN CHINA STAR OPTOELECTRONICE TECHNOLOGY CO., LTD
IPC: H01L27/12 , H01L29/66 , H01L29/786
CPC classification number: H01L27/1288 , H01L21/28 , H01L27/124 , H01L29/66765 , H01L29/78678
Abstract: An LTPS array substrate and a method for producing the same are proposed. The method includes: forming an insulating layer, a semiconductor layer, and a first positive photoresist layer on the substrate one by one; exposing one side of the substrate on the opposite side of the gate for forming a polycrystalline silicon layer; forming a source and a drain of the TFT on the polycrystalline silicon layer; forming a pixel electrode on the insulating layer and part of the source; forming a plain passivation layer on a source-drain electrode layer; forming a transparent electrode layer on the plain passivation layer so that the transparent electrode layer is connected to the gate, the source, and the drain via the contact hole. The use of masks in types and in numbers in the LTPS technology will be reduced. So, both of the processes and the production costs are reduced.
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公开(公告)号：US09761729B2
公开(公告)日：2017-09-12
申请号：US15058173
申请日：2016-03-02
Inventor： Peng Du , Cheng-hung Chen
IPC: H01L27/14 , H01L29/786 , H01L29/66
CPC classification number: H01L22/34 , H01L22/14 , H01L27/1244 , H01L27/127 , H01L29/66742 , H01L29/78609 , H01L29/78648 , H01L29/78696
Abstract: A thin-film transistor (TFT) switch includes a gate, a drain, a source, a semiconductor layer, and a fourth electrode. The drain is connected to a first signal. The gate is connected to a control signal to control the switch on or off. The source outputs the first signal when the switch turns on. The fourth electrode and the gate are respectively located at two sides of the semiconductor layer. The fourth electrode is conductive and is selectively coupled to different voltage levels, thereby reducing leakage current in a channel to improve switch characteristic when the switch turns off.
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公开(公告)号：US09507228B2
公开(公告)日：2016-11-29
申请号：US14416449
申请日：2014-07-04
Inventor： Cong Wang , Ming Hung Shih , Peng Du
IPC: G02F1/1362 , H01L27/12
CPC classification number: G02F1/136286 , G02F1/136209 , G02F2201/40 , H01L27/124 , H01L27/1255
Abstract: An array substrate belongs to the technical field of display technology and solves the technical problem of low aperture ratio of prior liquid crystal display device. The array substrate includes a plurality of sub pixel units arranged in an array and a plurality of signal lines, wherein one signal line of two adjacent signal lines is arranged in a first side of corresponding sub pixel units, and the other signal line is arranged in a second side of corresponding sub pixel units. The first side and the second side are one of opposite sides of the sub pixel units respectively. The array substrate can be used in liquid crystal television, liquid crystal display, mobile phone, tablet personal computer and other display devices.
Abstract translation: 阵列基板属于显示技术领域，解决了现有液晶显示装置的低开口率的技术问题。 阵列基板包括以阵列布置的多个子像素单元和多个信号线，其中两个相邻信号线的一个信号线被布置在相应的子像素单元的第一侧中，另一个信号线被布置在 相应子像素单元的第二侧。 第一侧和第二侧分别是子像素单元的相对侧之一。 阵列基板可用于液晶电视，液晶显示器，手机，平板电脑等显示装置。
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公开(公告)号：US09501961B2
公开(公告)日：2016-11-22
申请号：US14387754
申请日：2014-07-29
CPC classification number: G09G3/2003 , G09G3/2074 , G09G3/2085 , G09G2300/0426 , G09G2310/0202 , G09G2320/0223
Abstract: A display panel is disclosed. The display panel includes: at least one first data line, at least one second data line, at least two first pixel columns, and at least two second pixel columns. In two adjacent ones of subpixel rows, the first data line is electrically connected to one of first subpixels in one of the first pixel columns and one of second subpixels in one of the second pixel columns, and the second data line is electrically connected to one of the second subpixels in the one of the second pixel columns and one of the first subpixels in another one of the first pixel columns adjacent to the one of the second pixel columns.
Abstract translation: 公开了一种显示面板。 显示面板包括：至少一个第一数据线，至少一个第二数据线，至少两个第一像素列和至少两个第二像素列。 在两个相邻的子像素行中，第一数据线电连接到第一像素列之一和第二像素列之一中的第二子像素之一中的第一子像素之一，并且第二数据线电连接到一个 的所述第二像素列中的所述第二子像素和与所述第二像素列之一相邻的所述第一像素列中的所述第一子像素之一。
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Patent Agency Ranking
公开(公告)号：US20150022211A1
公开(公告)日：2015-01-22
申请号：US14241416
申请日：2014-01-17
Inventor： Peng Du , Je-Hao Hsu , Ming-hung Shih
IPC: G09G3/00
CPC classification number: G09G3/006
Abstract: The present disclosure provides a detection circuit for a display panel, comprising: a shorting bar, with connection lines for introducing a test signal or a control signal arranged thereon; a transistor array, the gates of which are connected to the connection lines for introducing the control signal, wherein the connection lines for introducing the test signal are connected with the data lines or the scanning lines of the display panel via the sources and the drains of transistors, under the control signal, and a component, arranged between the gates of the transistor array and the shorting bar, for further reducing or increasing a voltage or current of the gates so that the transistor array can be cut off reliably when the control signal is a signal enabling the transistor array to be cut off. The detection circuit can further reduce the channel length of the thus being advantageous for the design of the narrow frame.
Abstract translation: 本公开提供了一种用于显示面板的检测电路，包括：短路棒，具有用于引入测试信号或布置在其上的控制信号的连接线; 晶体管阵列，其栅极连接到用于引入控制信号的连接线，其中用于引入测试信号的连接线经由源和源的漏极与显示面板的数据线或扫描线连接 在控制信号下的晶体管以及配置在晶体管阵列和短路棒的栅极之间的部件，用于进一步减小或增加栅极的电压或电流，使得当控制信号 是能够切断晶体管阵列的信号。 检测电路可以进一步减小通道长度，从而有利于窄框架的设计。
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公开(公告)号：US10274793B2
公开(公告)日：2019-04-30
申请号：US15323975
申请日：2016-12-14
Inventor： Peng Du
IPC: G06F3/044 , G02F1/1343 , H01L27/12 , G02F1/1362 , G02F1/1368 , G02F1/1333 , G06F3/041
Abstract: The present disclosure provides a COA array substrate and a display device. The COA array substrate includes a plurality of gate lines; a plurality of data lines; and a plurality of pixel units. Each of the pixel units includes a pixel electrode and a common electrode. The common electrode includes a lower common electrode and an upper common electrode. The lower common electrode is disposed on one of the data lines, and the upper common electrode is disposed on one of the gate lines. The present disclosure solves a light leakage problem and problems that an aperture ratio and a transmittance are low in a liquid crystal panel.
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公开(公告)号：US10185193B2
公开(公告)日：2019-01-22
申请号：US15313131
申请日：2016-07-12
Inventor： Peng Du
IPC: G02F1/1362 , G02F1/1337 , G02F1/1343
Abstract: A liquid crystal pixel structure is disclosed. The liquid crystal pixel structure includes: a pixel electrode, located in a pixel aperture. The pixel electrode has two or more display domains applied with the same voltage level. The pixel electrode extends in different directions in the display domains. A gate line is located at an intersection of the display domains. An edge of the intersection of the display domains overlaps the gate line. A data line is located at an edge of the pixel aperture. The pixel electrode is controlled by the gate line and the data line via a transistor. The aperture of the pixel structure is divided by the gate lines. Therefore, the edge of the display domains overlaps the gate lines. The dark line can be covered by the gate lines and thus the aperture rate and the transparent rate can be raised.
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公开(公告)号：US10096293B2
公开(公告)日：2018-10-09
申请号：US14908403
申请日：2016-01-11
Inventor： Peng Du
Abstract: The present invention proposes a gate driver including a plurality of gate driver on array (GOA) units. Each of the GOA unit includes a main driving circuit, a starting signal output circuit, and a plurality of gate driving circuits. The gate driver utilizes a starting signal and two inversed clock signals to control the charging period and the discharging period of the gate driver. Furthermore, the gate driver utilizes multiple clock signals to control the output of the gate driving signals. In this way, the number of the clock signals is reduced and thus the power consumption is also reduced.
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公开(公告)号：US09972261B2
公开(公告)日：2018-05-15
申请号：US14907825
申请日：2016-01-11
Inventor： Xiaoxiao Wang , Peng Du
CPC classification number: G09G3/3648 , G09G3/3677 , G09G2230/00 , G09G2300/0408 , G09G2300/0452 , G09G2310/0251 , G09G2310/0286 , G09G2320/0242 , G11C19/28
Abstract: A GOA (Gate driver On Array) for an LCD (Liquid Crystal Display) device is disclosed herein. The LCD device comprises a plurality of scanning lines. The GOA circuit comprises a plurality of GOA units, which are cascaded with each other as a plurality of level GOA units. The (n)th level GOA unit comprises a clock circuit, a pull-down circuit, a bootstrap capacitor circuit, a pull-up circuit, and a pull-down sustain circuit, to improve the color shift issue of a Tri-gate.
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