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公开(公告)号：US09726955B2
公开(公告)日：2017-08-08
申请号：US14430205
申请日：2014-09-11
Inventor： Bo Sun , Hongyuan Xu , Hsiangchih Hsiao , Changi Su , Mian Zeng , Xiaoxiao Wang
IPC: G02F1/1368 , H01L21/12 , G02F1/136 , H01L21/84 , H01L27/12 , G02F1/1335 , G02F1/1343 , H01L21/02 , H01L21/027 , H01L21/285 , H01L29/66 , H01L29/786 , G02F1/1362 , G02F1/1333
CPC classification number: G02F1/1368 , G02F1/133514 , G02F1/134309 , G02F1/13439 , G02F1/136 , G02F1/136227 , G02F2001/133302 , G02F2001/133519 , G02F2001/136222 , H01L21/02422 , H01L21/02532 , H01L21/02592 , H01L21/0273 , H01L21/2855 , H01L21/84 , H01L27/12 , H01L27/1218 , H01L27/1222 , H01L27/1288 , H01L29/66765 , H01L29/78669
Abstract: The present invention provides a manufacture method of a TFT array substrate and a TFT array substrate structure, and the TFT array substrate structure comprises a substrate (1), a first metal electrode (2) on the substrate (1), a gate isolation layer (3) positioned on the substrate (1) and completely covering the first metal electrode (2), an island shaped semiconductor layer (4) on the gate isolation layer (3), a second metal electrode (6) on the gate isolation layer (3) and the island shaped semiconductor layer (4), a protecting layer (8) on the second metal electrode (6), a color resist layer (7) on the protecting layer (8), a protecting layer (12) on the color resist layer (7) and a first pixel electrode layer (9) on the protecting layer (12); a via (81) is formed on the protecting layer (8), the color resist layer (7) and the protecting layer (12), and an organic material layer (10) fills the inside of the via (81).
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2.发明授权LTPS TFT having dual gate structure and method for forming LTPS TFT 有权具有双栅极结构的LTPS TFT和用于形成LTPS TFT的方法公开(公告)号：US09437435B2
公开(公告)日：2016-09-06
申请号：US14415607
申请日：2014-11-14
Inventor： Xiaoxiao Wang , Hsiang Chih Hsiao , Peng Du , Chang-I Su , Hongyuan Xu , Bo Sun
IPC: H01L21/28 , H01L27/12 , H01L29/786 , H01L29/66 , H01L29/49 , H01L29/423
CPC classification number: H01L21/28114 , H01L21/28035 , H01L27/1222 , H01L27/1288 , H01L29/42384 , H01L29/4908 , H01L29/6675 , H01L29/78603 , H01L29/78648 , H01L29/78672
Abstract: The present invention proposes a low temperature poly-silicon thin-film transistor having a dual-gate structure and a method for forming the low temperature poly-silicon thin-film transistor. The low temperature poly-silicon thin-film transistor includes: a substrate, one or more patterned amorphous silicon (a-Si) layers, disposed in a barrier layer on the substrate, for forming a bottom gate, an NMOS disposed on the barrier layer, and a PMOS disposed on the barrier layer. The NMOS comprises a patterned gate electrode (GE) layer as a top gate, and the patterned GE layer and the bottom gate formed by the one or more patterned a-Si layers form a dual-gate structure. The present invention proposes a low temperature poly-silicon thin-film transistor with a more stabilized I-V characteristic, better driving ability, low power consumption, and higher production yield.
Abstract translation: 本发明提出了一种具有双栅极结构的低温多晶硅薄膜晶体管和形成低温多晶硅薄膜晶体管的方法。 低温多晶硅薄膜晶体管包括：基板，设置在基板上的阻挡层中的一个或多个图案化非晶硅（a-Si）层，用于形成底栅，设置在势垒层上的NMOS 和设置在阻挡层上的PMOS。 NMOS包括作为顶栅的图案化栅电极（GE）层，并且由一个或多个图案化a-Si层形成的图案化GE层和底栅形成双栅结构。 本发明提出了具有更稳定的I-V特性，更好的驱动能力，低功耗和更高的产量的低温多晶硅薄膜晶体管。
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公开(公告)号：US09972261B2
公开(公告)日：2018-05-15
申请号：US14907825
申请日：2016-01-11
Inventor： Xiaoxiao Wang , Peng Du
CPC classification number: G09G3/3648 , G09G3/3677 , G09G2230/00 , G09G2300/0408 , G09G2300/0452 , G09G2310/0251 , G09G2310/0286 , G09G2320/0242 , G11C19/28
Abstract: A GOA (Gate driver On Array) for an LCD (Liquid Crystal Display) device is disclosed herein. The LCD device comprises a plurality of scanning lines. The GOA circuit comprises a plurality of GOA units, which are cascaded with each other as a plurality of level GOA units. The (n)th level GOA unit comprises a clock circuit, a pull-down circuit, a bootstrap capacitor circuit, a pull-up circuit, and a pull-down sustain circuit, to improve the color shift issue of a Tri-gate.
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公开(公告)号：US10192902B2
公开(公告)日：2019-01-29
申请号：US15853832
申请日：2017-12-24
Applicant: Shenzhen China Star Optoelectronics Technology Co., Ltd. , Wuhan China Star Optoelectronics Technology Co., Ltd.
Inventor： Cong Wang , Peng Du , Xiaoxiao Wang
IPC: H01L27/12 , G02F1/1368 , H01L29/786
Abstract: A method for manufacturing a LTPS array substrate includes: forming a source electrode and a drain electrode on a substrate, forming a poly-silicon layer in a first region and a second region of the substrate including the source electrode and the drain electrode, such that the poly-silicon layer of the first region has a thickness greater than that of the second region and the poly-silicon layer of the first region partially covers the source electrode and the drain electrode; passivating a surface of the poly-silicon layer in order to turn a part of the poly-silicon layer of the second region and the first region that is adjacent to the surface into an insulating layer; and forming a gate electrode on the insulating layer between the source electrode and the drain electrode. The LTPS technical process is simple and can reduce the producing costs.
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公开(公告)号：US10297216B2
公开(公告)日：2019-05-21
申请号：US14907930
申请日：2016-01-12
Inventor： Xiaoxiao Wang , Peng Du
IPC: G09G3/20 , G09G3/36 , G02F1/13 , G02F1/1345 , G02F1/1362
Abstract: A gate driving circuit and an array substrate using the same are described. The gate driving circuit pulls up and pulls down the voltage level of the node in one display frame by a first voltage signal of a second driving module and a second voltage signal of a third driving module to control the high level and low level respectively of scan signal in the scan output terminal for sequentially writing data signal to all the first row sub-pixels, all the second row sub-pixels and all the third row sub-pixels of the one display frame in order to prevent the sub-pixels from RC delay and color deviation, thereby improving the display quality of the LCD.
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Patent Agency Ranking
公开(公告)号：US09905590B2
公开(公告)日：2018-02-27
申请号：US14779089
申请日：2015-07-31
Applicant: Shenzhen China Star Optoelectronics Technology Co., Ltd. , Wuhan China Star Optoelectronics Technology Co., Ltd.
Inventor： Cong Wang , Peng Du , Xiaoxiao Wang
IPC: H01L27/12 , H01L29/786 , G02F1/1368
CPC classification number: H01L27/127 , G02F1/1368 , G02F2202/104 , H01L27/1222 , H01L27/1248 , H01L27/1288 , H01L29/78621 , H01L29/78675
Abstract: The present invention provides a LTPS array substrate and a manufacturing method thereof. The method comprises: forming a source electrode and a drain electrode on a substrate, forming polysilicon layers of a first region and a second region on the substrate including the source electrode and the drain electrode, and the thickness of the polysilicon layer of the first region is greater than the one of the second region, the polysilicon layer of the first region partially covers the source electrode and the drain electrode; passivating the surface of the polysilicon layer in order to turn the part of the adjacent surface of the polysilicon layer of the second region and the first region into an insulating layer; forming a gate electrode on the insulating layer between the source electrode and the drain electrode. The present invention can simplify the LTPS technical process and reduce the producing costs.
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公开(公告)号：US09865619B2
公开(公告)日：2018-01-09
申请号：US14779545
申请日：2015-08-13
Inventor： Xiaoxiao Wang , Peng Du , Cong Wang
IPC: H01L27/12 , H01L29/786 , H01L21/02 , H01L21/3213 , H01L29/45 , H01L29/66 , H01L21/22 , H01L21/265 , G02F1/1368
CPC classification number: H01L27/1222 , G02F1/136209 , G02F1/1368 , G02F2202/104 , H01L21/02164 , H01L21/02238 , H01L21/02532 , H01L21/02592 , H01L21/22 , H01L21/26513 , H01L21/32133 , H01L27/1218 , H01L27/124 , H01L27/127 , H01L27/1288 , H01L29/458 , H01L29/66757 , H01L29/786 , H01L29/78633 , H01L29/78675
Abstract: An array substrate and a manufacturing method thereof are provided. The method has steps of: forming a buffer layer, a light-shading layer, and a whole semiconductor layer on a substrate; simultaneously patterning the semiconductor layer and the light-shading layer; and forming a first insulation layer, a first metal layer, a second insulation layer, a second metal layer, a flat layer, and a first transparent conductive layer on the patterned semiconductor layer.
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公开(公告)号：US20150185548A1
公开(公告)日：2015-07-02
申请号：US14241075
申请日：2014-01-21
Inventor： Hongyuan Xu , Hsiangchih Hsiao , Changi Su , Mian Zeng , Xiaoxiao Wang
IPC: G02F1/1335 , H01L29/786 , H01L27/12
CPC classification number: G02F1/133514 , G02F1/136213 , G02F1/13624 , H01L27/124 , H01L27/1255 , H01L29/78669
Abstract: The present invention provides a TFT substrate and a liquid crystal display panel using the TFT substrate. The TFT substrate includes: first and second sharing capacitors (2, 4) that are connected in parallel. The first sharing capacitor (2) includes a first upper substrate (22), a first lower substrate (24) opposite to the first upper substrate (22), and a first semiconductor layer (26) arranged between the first upper substrate (22) and the first lower substrate (24). The second sharing capacitor (4) includes a second upper substrate (42), a second lower substrate (44) opposite to the second upper substrate (42), and a second semiconductor layer (46) arranged between the second upper substrate (42) and the second lower substrate (44). The first upper substrate (22) of the first sharing capacitor (2) and the second lower substrate (44) of the second sharing capacitor (4) are electrically connected to the pixel electrode (6). The second upper substrate (42) of the second sharing capacitor (4) is electrically connected to the Com trace (8).
Abstract translation: 本发明提供一种TFT基板和使用该TFT基板的液晶显示面板。 TFT基板包括：并联连接的第一和第二共享电容器（2,4）。 第一共享电容器（2）包括第一上基板（22），与第一上基板（22）相对的第一下基板（24）和布置在第一上基板（22）之间的第一半导体层（26） 和第一下基板（24）。 第二共享电容器（4）包括第二上基板（42），与第二上基板（42）相对的第二下基板（44）和布置在第二上基板（42）之间的第二半导体层（46） 和第二下基板（44）。 第一共享电容器（2）的第一上基板（22）和第二共享电容器（4）的第二下基板（44）电连接到像素电极（6）。 第二共享电容器（4）的第二上基板（42）电连接到Com迹线（8）。
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9.发明授权公开(公告)号：US10564485B2
公开(公告)日：2020-02-18
申请号：US15575294
申请日：2017-07-20
Inventor： Xiaoxiao Wang , Peng Du
IPC: G02F1/1339 , G02F1/1362 , G02F1/1333
Abstract: The present invention provides a liquid crystal display panel, which comprises a color film substrate, an array substrate and a liquid crystal layer sandwiched between the color film substrate and the array substrate, said array substrate has a pixel electrode where a surface is disposed with a number of recesses and a number of terraces, said number of recesses and said number of terraces are disposed in evenly intersectional arrangement, said respective recess is located at a position between two interconnected pixels, said respective recess is disposed with a first spacer, said respective terrace is disposed with a second spacer, a height of said first spacer protruded from said terrace is larger than a height of said second spacer protruded from said terrace, said first spacers and said second spacers are extended into the liquid crystal layer, for support of between said color film substrate and said array substrate.
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10.发明授权公开(公告)号：US10008170B2
公开(公告)日：2018-06-26
申请号：US14905879
申请日：2015-12-30
Inventor： Xiaoxiao Wang , Peng Du
IPC: G09G3/36
CPC classification number: G09G3/3677 , G09G3/3696 , G09G2300/0809 , G09G2310/0286 , G11C19/28
Abstract: The present invention proposes a GOA circuit and a display device adopting the same. The GOA circuit includes thirteen transistors and a first capacitor. The GOA circuit can be driven in 2D and 3D driving modes to prolong charging time of each pixel. Each two GOA circuit units share a set of Nth stage start pulse signals, Nth stage gate pulse signals and eight clock pulse signals. Because the charging time of each pixel is prolonged, the display device can show images with better display quality.
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