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公开(公告)号:US06927356B2
公开(公告)日:2005-08-09
申请号:US10753080
申请日:2004-01-08
申请人: Shinji Sato , Kenichi Koyama , Masahiro Arioka
发明人: Shinji Sato , Kenichi Koyama , Masahiro Arioka
IPC分类号: H02B13/02 , H01H33/56 , H01H33/66 , H01H33/666
CPC分类号: H01H33/666 , H01H33/565 , H01H33/6661 , H01H2033/6667
摘要: In a switchgear, oscillation of a moving current-carrying shaft and a moving contact of a vacuum valve is minimized, offset load on the contact surface is reduced, and friction the portion supporting the moving current-carrying shaft is reduced. A vacuum valve is disposed in a gas tank, one end of a moving current-carrying shaft integrally includes a moving contact of the vacuum valve, and a contact pressure adjusting spring is disposed on the other end of the moving current-carrying shaft. An operating rod extends through the gas tank, an operation mechanism is mounted on the operating rod outside the gas tank, an insulating rod is mounted inside the gas tank, and the contact pressure adjusting spring is joined to the insulating rod.
摘要翻译: 在开关装置中,移动载流轴的振荡和真空阀的移动接触被最小化,接触表面上的偏移负载减小,并且支撑移动载流轴的部分的摩擦减小。 真空阀设置在气罐中,移动载流轴的一端一体地包括真空阀的移动触点,并且接触压力调节弹簧设置在移动载流轴的另一端。 操作杆延伸穿过气罐,操作机构安装在气罐外侧的操作杆上,绝缘杆安装在气罐内,接触压力调节弹簧与绝缘杆接合。
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公开(公告)号:US6142016A
公开(公告)日:2000-11-07
申请号:US338194
申请日:1994-11-09
申请人: Kouji Kobayashi , Shinji Sato , Takeo Kojima , Nobuyuki Tanaka , Michio Shimura
发明人: Kouji Kobayashi , Shinji Sato , Takeo Kojima , Nobuyuki Tanaka , Michio Shimura
CPC分类号: G01F23/22 , G03G15/0848 , G03G15/0856
摘要: Disclosed is a toner residual quantity detecting apparatus for detecting a residual quantity of toners in a developing unit. This toner residual quantity detecting apparatus has a temperature sensor, provided in the bottom of the developing unit, for generating an output proportional to a detected temperature and a detecting circuit for detecting the toner residual quantity from the output of the temperature sensor. This temperature sensor detects a difference between temperatures when covered with the toners and when not covered with the toners, thereby detecting the toner residual quantity.
摘要翻译: 公开了一种用于检测显影单元中的调色剂的剩余量的调色剂剩余量检测装置。 该调色剂剩余量检测装置具有设置在显影单元的底部的用于产生与检测温度成比例的输出的温度传感器和用于从温度传感器的输出检测调色剂剩余量的检测电路。 该温度传感器检测到当用调色剂覆盖时的温度差异,并且当不被调色剂覆盖时,检测调色剂剩余量。
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公开(公告)号:US6121178A
公开(公告)日:2000-09-19
申请号:US944095
申请日:1997-10-02
申请人: Kohichiro Eshima , Kouki Toishi , Katsuaki Okabe , Tsuyoshi Nishimura , Shinji Sato , Choju Nagata
发明人: Kohichiro Eshima , Kouki Toishi , Katsuaki Okabe , Tsuyoshi Nishimura , Shinji Sato , Choju Nagata
IPC分类号: C04B35/64 , C01G19/00 , C04B35/457 , C23C14/08 , C23C14/34 , C30B29/22 , C04B35/453
CPC分类号: C23C14/3414 , C04B35/457
摘要: Sintered ITO having a relative density of at least 88% and an oxygen content of 15.5-17.0 wt %, as well as an ITO sputtering target made of this sintered ITO. Using the target, an optimal range for the proportion of oxygen in a mixture of argon and oxygen gases used as a sputtering atmosphere is sufficiently expanded to permit the consistent formation of ITO films.
摘要翻译: 具有至少88%的相对密度和15.5-17.0重量%的氧含量的烧结ITO以及由该烧结的ITO制成的ITO溅射靶。 使用目标,用作溅射气氛的氩气和氧气的混合物中的氧气比例的最佳范围被充分地扩大以允许ITO膜的一致的形成。
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公开(公告)号:US6038244A
公开(公告)日:2000-03-14
申请号:US16282
申请日:1998-01-30
申请人: Akaru Usui , Shinji Sato , Hisao Tanaka
发明人: Akaru Usui , Shinji Sato , Hisao Tanaka
IPC分类号: H01S3/094 , H01S3/0941 , H01S3/091
CPC分类号: H01S3/0941 , H01S3/025 , H01S3/094057 , H01S3/094084
摘要: A semiconductor excitation solid-state laser apparatus, in which a cross-sectional area of an optical guide plate leading an excited beam emitted from a semiconductor laser element to a solid-state laser medium is made larger in the side of the semiconductor laser element thereof, while a cross-sectional area thereof is made smaller in the side of the solid-state laser medium.
摘要翻译: 半导体激光固态激光装置,其中将从半导体激光元件发射的激发光束引导到固态激光介质的导光板的横截面积在其半导体激光元件的侧面较大 而在固态激光介质的侧面的横截面积较小。
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公开(公告)号:US5841645A
公开(公告)日:1998-11-24
申请号:US841388
申请日:1997-04-30
申请人: Shinji Sato
发明人: Shinji Sato
CPC分类号: H02M7/487
摘要: A multi-level inverter, including an AC output terminal, at least four DC input terminals with different potentials having a first DC input terminal with a maximum potential and a second DC input terminal with a minimum potential, a positive arm connected between the first DC input terminal and the AC output terminal, and a negative arm connected between the second DC input terminal and the AC output terminal. Each of the positive and negative arms is composed of a plurality of series connected switching devices, respectively. The multi-level inverter further includes a plurality of clamp diodes, each connected between one of the DC input terminals other than the first and second DC input terminals and one of the positive and negative arms, respectively, a plurality of first snubber circuits, each composed of a series circuit of a snubber capacitor and a snubber diode and connected in parallel with one of the switching devices, respectively, and a plurality of discharging circuits, each composed of at least a resistor and connected between one of the first snubber circuits and the DC input terminals, respectively.
摘要翻译: 一种包括AC输出端子的多电平逆变器,具有不同电位的至少四个DC输入端子,具有具有最大电位的第一DC输入端子和具有最小电位的第二DC输入端子,正极臂连接在第一DC 输入端子和交流输出端子,以及连接在第二直流输入端子和交流输出端子之间的负极。 正极和负极中的每一个分别由多个串联连接的开关装置组成。 多电平逆变器还包括多个钳位二极管,每个钳位二极管分别连接在除了第一和第二DC输入端子之外的一个DC输入端子和正极和负极臂中的一个之间,多个第一缓冲电路,每个 由缓冲电容器和缓冲二极管的串联电路分别与一个开关装置并联连接的多个放电电路,以及多个放电电路,每个放电电路由至少一个电阻器组成,并连接在第一缓冲电路之一和 直流输入端子。
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公开(公告)号:US5768325A
公开(公告)日:1998-06-16
申请号:US591129
申请日:1996-01-25
申请人: Rieko Yamamoto , Shinji Sato
发明人: Rieko Yamamoto , Shinji Sato
摘要: A delay circuit externally adjustable for the delay time "n" as desired, which comprises a FIFO (FIRST-IN, FIRST-OUT) type memory, a self-load counter, and a decoder circuit. In addition to a data signal, an input clock is inputted to the memory as the write clock and the read clock. The self-load counter operates in synchronization with the input clock, and loads a setting of a load value-designating signal at a prescribed number of counts. The decoder circuit receives the output of the self-load counter which has a prescribed cycle, and outputs a reset signal with the same cycle to the memory. This cycle determines the delay time. The delay circuit allows a greatly reduced number of ICs used as compared with the prior art, even for increased delay times.
摘要翻译: 延迟电路根据需要外部可调节延迟时间“n”,其包括FIFO(FIRST-IN,FIRST-OUT)型存储器,自负载计数器和解码器电路。 除了数据信号之外,输入时钟作为写时钟和读时钟输入到存储器。 自负载计数器与输入时钟同步工作,并以规定数量的计数加载负载值指定信号的设置。 解码器电路接收具有规定周期的自负载计数器的输出,并将相同周期的复位信号输出到存储器。 该周期决定延迟时间。 与现有技术相比,延迟电路允许大大减少使用的IC数量,即使增加延迟时间。
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公开(公告)号:US5563122A
公开(公告)日:1996-10-08
申请号:US244758
申请日:1994-09-06
申请人: Ken Endo , Shinji Sato , Yoshinori Sugiyama , Masaru Ohno , Hideo Sakakibara
发明人: Ken Endo , Shinji Sato , Yoshinori Sugiyama , Masaru Ohno , Hideo Sakakibara
CPC分类号: A61K9/0019 , A61K38/29 , A61K47/02 , A61K47/26 , A61K9/19 , Y10S514/97
摘要: A safe, stabilized lyophilized preparation comprising parathyroid hormone (PTH) as an active ingredient and effective amounts of sugar and sodium chloride to provide a stable preparation of parathyroid hormone.
摘要翻译: PCT No.PCT / JP92 / 01599 Sec。 371日期:1994年9月26日 102(e)日期1994年9月26日PCT提交1992年12月8日PCT公布。 第WO92 / 01599号公报 日期1993年6月24日一种安全,稳定的冻干制剂,其包含甲状旁腺激素(PTH)作为活性成分和有效量的糖和氯化钠以提供甲状旁腺激素的稳定制备。
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公开(公告)号:US5246528A
公开(公告)日:1993-09-21
申请号:US890195
申请日:1992-05-29
申请人: Fumihiko Hasegawa , Shinji Sato
发明人: Fumihiko Hasegawa , Shinji Sato
IPC分类号: H01L21/00
CPC分类号: H01L21/67086 , H01L21/67023 , H01L21/67075
摘要: An automatic wafer etching apparatus including a first elevator and a second elevator each having a top surface whose vertical cross-section is circularly concaved having a curvature equal to that of the wafers and adapted to reciprocate vertically such that the top surface can pass through the etching drum, and an etching drum having a main housing consisting of a pair of vertical parallel side plates opposing each other, a horizontal shaft integral with the main housing side plates; a plurality of rollers borne between the main housing side plates in a manner such that they are freely rotatory; the rollers having annular grooves in their surfaces to receive edges of wafers in a manner such that the wafers are supported vertically at suitable intervals in a horizontal row; small-diameter gears locked at those ends of the rollers.
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公开(公告)号:US5107438A
公开(公告)日:1992-04-21
申请号:US473035
申请日:1990-01-31
申请人: Shinji Sato
发明人: Shinji Sato
IPC分类号: H02J9/06 , H02M7/5395
CPC分类号: H02J9/062 , H02M7/5395
摘要: A control apparatus for an inverter including a filter consisting of a reactor and a capacitor, connected to the output terminal thereof is operative to compute such a voltage correction value to cancel a voltage difference between the reference voltage and the output voltage to add, to the voltage correction value, a value obtained by delaying the voltage correction value by one period of the inverter output voltage to prepare a reference correction value to correct the reference voltage by the reference correction value, thus to prepare a volatge command for control of the inverter. The voltage control based on the reference correction value is carried out in a feed-forward manner, thus making it possible to effectively eliminate voltage distortion appearing periodically in synchronization with the output voltage.
摘要翻译: 用于逆变器的控制装置包括连接到其输出端的由电抗器和电容器组成的滤波器,用于计算这种电压校正值以消除参考电压和输出电压之间的电压差, 电压校正值,通过将电压校正值延迟一倍的逆变器输出电压而获得的值,以准备参考校正值,以通过参考校正值校正参考电压,从而准备用于控制逆变器的挥发命令。 基于参考校正值的电压控制以前馈方式进行,从而可以有效地消除与输出电压同步的周期性出现的电压失真。
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公开(公告)号:US4611236A
公开(公告)日:1986-09-09
申请号:US628316
申请日:1984-07-06
申请人: Shinji Sato
发明人: Shinji Sato
IPC分类号: H01L27/092 , H01L21/82 , H01L21/8238 , H01L27/118 , H01L27/10 , H01L27/02
CPC分类号: H01L21/82 , H01L27/11807 , Y10S257/923
摘要: A masterslice semiconductor device has two kinds of basic cells including a first one having the same size same as that of ordinary basic cells in a prior art masterslice semiconductor device and a second one having a size larger than that of the first basic cell. A number of the large-sized basic cells are arranged along columns of a semiconductor substrate and constitute a plurality of basic cell arrays which are disposed along rows of the semiconductor substrate. Each of the basic cell arrays of the second basic cells is situated between two adjacent basic cell arrays of the first basic cells. Each of the regions occupied by the basic arrays of the second basic cells can be used for distributing interconnecting lines as in the prior art masterslice semiconductor device. At least one of the second basic cells in each of the regions serves to interconnect the first basic cells in adjacent basic cell arrays, and also provides an elementary circuit block, that is a unit cell, in conjunction with the first basic cells.
摘要翻译: 主板半导体器件具有两种基本单元,其包括与现有技术的主板半导体器件中的普通基本单元具有相同尺寸的第一基本单元,而第二基本单元的尺寸大于第一基本单元的大小。 许多大型基体单元沿着半导体衬底的列布置,并且构成沿着半导体衬底的行设置的多个基本单元阵列。 第二基本单元的每个基本单元阵列位于第一基本单元的两个相邻基本单元阵列之间。 由第二基本单元的基本阵列占据的每个区域可以用于分配互连线,如现有技术的主机半导体器件。 每个区域中的第二基本单元中的至少一个用于互连相邻基本单元阵列中的第一基本单元,并且还提供与第一基本单元相结合的基本电路块,即单位单元。
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