公开(公告)号：US20220317878A1

公开(公告)日：2022-10-06

申请号：US17671602

申请日：2022-02-15

Applicant: Silicon Motion, Inc.

Inventor： Ching-Hui Lin

IPC: G06F3/06 ,  G06F12/02 ,  G06F12/1009

Abstract: The present invention provides a control method of the flash memory controller. In the control method, after receiving a deallocate command from a host device, the flash memory controller will update a valid page count table, a detailed valid page count table and/or a zone valid page count table according to deallocate command, for the flash memory controller to efficiently and quickly determine if any one of the zones does not have any valid data, so that the flash memory controller can recommend the host device to send a reset command to reset the zone.

公开(公告)号：US20220066687A1

公开(公告)日：2022-03-03

申请号：US17199388

申请日：2021-03-11

Applicant: Silicon Motion, Inc.

Inventor： Ching-Hui Lin

IPC: G06F3/06

Abstract: A control method of a flash memory controller, wherein the control method includes the steps of: when data is written to a page of any block of a flash memory module, recording a write time in the page; create a write time table, wherein the write time table records block numbers of blocks having data written therein and corresponding write time; compress the write time table to generate a compressed write time table, wherein the compressed write time table contains multiple time ranges and corresponding indexes, each index corresponds to a page of the flash memory module, and the page records block numbers of all blocks whose writing time is within the corresponding time range.

公开(公告)号：US10163499B2

公开(公告)日：2018-12-25

申请号：US15431643

申请日：2017-02-13

Applicant: Silicon Motion Inc.

Inventor： Ching-Hui Lin ,  Tsung-Chieh Yang

IPC: G11C16/04 ,  G11C11/56 ,  G11C16/10

Abstract: A control device for writing data into a flash memory unit includes a determining circuit and a writing circuit. The determining circuit is arranged to determine a data polarity of an n-th data bit of the flash memory unit when writing data into the flash memory unit for the n-th time. The writing circuit is arranged to inject an n-th electrical charge amount to a floating gate of the flash memory unit according to the data polarity of the n-th data bit only. The determining circuit is further arranged to determine the data polarity of an (n+1)-th data bit of the flash memory unit when writing data into the flash memory unit for the (n+1)-th time. The writing circuit is further arranged to selectively inject an (n+1)-th electrical charge amount to the floating gate of the flash memory unit according to the data polarity of the (n+1)-th data bit only.

公开(公告)号：US20170169884A1

公开(公告)日：2017-06-15

申请号：US15431643

申请日：2017-02-13

Applicant: Silicon Motion Inc.

Inventor： Ching-Hui Lin ,  Tsung-Chieh Yang

IPC: G11C11/56

CPC classification number: G11C11/5635 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/10

Abstract: A control device for writing data into a flash memory unit includes a determining circuit and a writing circuit. The determining circuit is arranged to determine a data polarity of an n-th data bit of the flash memory unit when writing data into the flash memory unit for the n-th time. The writing circuit is arranged to inject an n-th electrical charge amount to a floating gate of the flash memory unit according to the data polarity of the n-th data bit only. The determining circuit is further arranged to determine the data polarity of an (n+1)-th data bit of the flash memory unit when writing data into the flash memory unit for the (n+1)-th time. The writing circuit is further arranged to selectively inject an (n+1)-th electrical charge amount to the floating gate of the flash memory unit according to the data polarity of the (n+1)-th data bit only.

公开(公告)号：US09588709B2

公开(公告)日：2017-03-07

申请号：US14983566

申请日：2015-12-30

Applicant: Silicon Motion Inc.

Inventor： Tsung-Chieh Yang ,  Chun-Chieh Kuo ,  Ching-Hui Lin ,  Yang-Chih Shen

IPC: G11C16/04 ,  G06F12/02 ,  G06F3/06

CPC classification number: G06F3/0634 ,  G06F3/0604 ,  G06F3/064 ,  G06F3/0679 ,  G06F12/0246 ,  G06F2212/7201 ,  G06F2212/7206 ,  G11C11/5628 ,  G11C11/5642 ,  Y02D10/13

Abstract: A flash memory controller for controlling a flash memory module includes a communication interface for receiving a first data and a second data; and a processing circuit for dynamically controlling a data writing mode of the flash memory module according to an amount of stored data in the flash memory module. If the amount of stored data in the flash memory module is less than a first threshold when the communication interface receives the first data, the processing circuit controls the flash memory module so that the first data is written into the first data block under an one-bit-per-cell mode. If the amount of stored data in the flash memory module is greater than the first threshold when the communication interface receives the second data, the processing circuit controls the flash memory module so that the second data is written into the second data block under a two-bit-per-cell mode.

Abstract translation: 一种用于控制闪速存储器模块的闪存控制器包括用于接收第一数据和第二数据的通信接口; 以及处理电路，用于根据闪速存储器模块中存储的数据量来动态地控制闪存模块的数据写入模式。 如果在通信接口接收到第一数据时闪存模块中存储的数据量小于第一阈值，则处理电路控制闪存模块，使得第一数据被写入第一数据块， 每单元位数模式。 如果在通信接口接收到第二数据时闪存模块中存储的数据量大于第一阈值，则处理电路控制闪存模块，使得第二数据被写入第二数据块， 每单元位数模式。

公开(公告)号：US20150127894A1

公开(公告)日：2015-05-07

申请号：US14596236

申请日：2015-01-14

Applicant: Silicon Motion Inc.

Inventor： Tsung-Chieh Yang ,  Chun-Chieh Kuo ,  Ching-Hui Lin ,  Yang-Chih Shen

IPC: G06F12/02

CPC classification number: G06F3/0634 ,  G06F3/0604 ,  G06F3/064 ,  G06F3/0679 ,  G06F12/0246 ,  G06F2212/7201 ,  G06F2212/7206 ,  G11C11/5628 ,  G11C11/5642 ,  Y02D10/13

Abstract: A flash memory controller for controlling a flash memory module includes a communication interface for receiving a first data and a second data; and a processing circuit for dynamically controlling a data writing mode of the flash memory module according to an amount of stored data in the flash memory module. If the amount of stored data in the flash memory module is less than a first threshold when the communication interface receives the first data, the processing circuit controls the flash memory module so that the first data is written into the first data block under an one-bit-per-cell mode. If the amount of stored data in the flash memory module is greater than the first threshold when the communication interface receives the second data, the processing circuit controls the flash memory module so that the second data is written into the second data block under a two-bit-per-cell mode.

Abstract translation: 一种用于控制闪速存储器模块的闪存控制器包括用于接收第一数据和第二数据的通信接口; 以及处理电路，用于根据闪速存储器模块中存储的数据量来动态地控制闪存模块的数据写入模式。 如果在通信接口接收到第一数据时闪存模块中存储的数据量小于第一阈值，则处理电路控制闪存模块，使得第一数据被写入第一数据块， 每单元位数模式。 如果在通信接口接收到第二数据时闪存模块中存储的数据量大于第一阈值，则处理电路控制闪存模块，使得第二数据被写入第二数据块， 每单元位数模式。

公开(公告)号：US08644071B2

公开(公告)日：2014-02-04

申请号：US13658086

申请日：2012-10-23

Applicant: Silicon Motion, Inc.

Inventor： Tsung-Chieh Yang ,  Ching-Hui Lin ,  Yang-Chih Shen ,  Chun-Chieh Kuo

IPC: G11C16/06

CPC classification number: G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C2211/5641

Abstract: The invention provides a flash memory apparatus. In one embodiment, the flash memory apparatus comprises a flash memory and a flash memory controller. The flash memory comprises a write circuit and a memory cell array comprising a plurality of memory cells, wherein the write circuit is coupled to the memory cell array to write data in the memory cells. The flash memory controller is coupled to the write circuit, obtains a total capacity and a used data amount of the flash memory, and directs the write circuit to perform data writing in a one-bit mode when a ratio of the user data amount to the total capacity is less than a first predetermined value.

Abstract translation: 本发明提供一种闪存装置。 在一个实施例中，闪存装置包括闪速存储器和闪存控制器。 闪速存储器包括写电路和包括多个存储单元的存储单元阵列，其中写电路耦合到存储单元阵列以将数据写入存储单元。 闪速存储器控制器耦合到写入电路，获得闪存的总容量和使用的数据量，并且当用户数据量与存储器的比率相对应时，引导写入电路以一位模式执行数据写入 总容量小于第一预定值。

公开(公告)号：US20220318157A1

公开(公告)日：2022-10-06

申请号：US17582010

申请日：2022-01-24

Applicant: Silicon Motion, Inc.

Inventor： Ken-Fu Hsu ,  Ching-Hui Lin

IPC: G06F12/1009 ,  G06F12/06

Abstract: The present invention provides a control method of the flash memory controller. In the control method, by establishing a valid page count table, a detailed valid page count table and/or a zone valid page count table according to deallocate command from the host device, the flash memory controller can efficiently and quickly determine if any one of the zones does not have any valid data, so that the flash memory controller can recommend the host device to send a reset command to reset the zone. In addition, after receiving the reset command from the host device, the flash memory controller can use a garbage collection operation or directly put the blocks corresponding to the erased zone into a spare block pool, for the further use.

公开(公告)号：US20220214808A1

公开(公告)日：2022-07-07

申请号：US17394401

申请日：2021-08-05

Applicant: Silicon Motion, Inc.

Inventor： Ching-Hui Lin

IPC: G06F3/06

Abstract: The present invention provides a control method of a flash memory controller, wherein the flash memory controller is configured to access a flash memory module, and the control method includes the steps of : receiving a settling command from a host device to configure a portion space of the flash memory module as a zoned namespace; receiving a write command from the host device to write data corresponding a first zone into a plurality of blocks of the flash memory module, wherein an access mode chose by the flash memory controller is determined based on a size of each zone and a size of each block.

公开(公告)号：US11048421B2

公开(公告)日：2021-06-29

申请号：US17030392

申请日：2020-09-24

Applicant: Silicon Motion, Inc.

Inventor： Tsung-Chieh Yang ,  Chun-Chieh Kuo ,  Ching-Hui Lin ,  Yang-Chih Shen

IPC: G11C11/34 ,  G11C16/04 ,  G06F3/06 ,  G06F12/02 ,  G11C11/56

Abstract: A flash memory controller for controlling a flash memory module includes a communication interface for receiving a first data and a second data; and a processing circuit for dynamically controlling a data writing mode of the flash memory module according to an amount of stored data in the flash memory module. If the amount of stored data in the flash memory module is less than a first threshold when the communication interface receives the first data, the processing circuit controls the flash memory module so that the first data is written into the first data block under an one-bit-per-cell mode. If the amount of stored data in the flash memory module is greater than the first threshold when the communication interface receives the second data, the processing circuit controls the flash memory module so that the second data is written into the second data block under a two-bit-per-cell mode.